(SLL <typ.UInt32> (ZeroExt8to32 val)
			(SLLconst <typ.UInt32> [3]
				(ANDconst <typ.UInt32> [3] ptr))) mem)

// AtomicAnd8(ptr,val)  =>  LoweredAtomicAnd(ptr&^3,(uint32(val) << ((ptr & 3) * 8)) | ^(uint32(0xFF) << ((ptr & 3) * 8))))
(AtomicAnd8  ptr val mem) && !config.BigEndian =>
	(LoweredAtomicAnd (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr)
		(OR <typ.UInt32> (SLL <typ.UInt32> (ZeroExt8to32 val)
			(SLLconst <typ.UInt32> [3]

		// atomic and/or.
		// *arg0 &= (|=) arg1. arg2=mem. returns memory.
		// SYNC
		// LL	(Rarg0), Rtmp
		// AND	Rarg1, Rtmp
		// SC	Rtmp, (Rarg0)
		// BEQ	Rtmp, -3(PC)
		// SYNC
		{name: "LoweredAtomicAnd", argLength: 3, reg: gpstore, asm: "AND", faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},

(AtomicCompareAndSwap(32|64)Variant ...) => (LoweredAtomicCas(32|64)Variant      ...)

// Return old contents.
(AtomicAnd(64|32|8)            ...) => (LoweredAtomicAnd(64|32|8)            ...)
(AtomicOr(64|32|8)             ...) => (LoweredAtomicOr(64|32|8)             ...)
(AtomicAnd(64|32|8)Variant     ...) => (LoweredAtomicAnd(64|32|8)Variant     ...)
(AtomicOr(64|32|8)Variant      ...) => (LoweredAtomicOr(64|32|8)Variant      ...)

// Write barrier.

(AtomicCompareAndSwap(32|64) ptr old new_ mem) => (LoweredAtomicCas(32|64) [1] ptr old new_ mem)
(AtomicCompareAndSwapRel32   ptr old new_ mem) => (LoweredAtomicCas32 [0] ptr old new_ mem)

(AtomicAnd(8|32)  ...) => (LoweredAtomicAnd(8|32)  ...)
(AtomicOr(8|32)   ...) => (LoweredAtomicOr(8|32)   ...)

(Slicemask <t> x) => (SRADconst (NEG <t> x) [63])
(ANDconst [1] z:(SRADconst [63] x)) && z.Uses == 1  => (SRDconst [63] x)

	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	config := b.Func.Config
	typ := &b.Func.Config.Types
	// match: (AtomicAnd8 ptr val mem)
	// cond: !config.BigEndian

			},
			outputs: []outputInfo{
				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
			},
		},
	},
	{
		name:           "LoweredAtomicAnd",
		argLen:         3,
		faultOnNilArg0: true,
		hasSideEffects: true,
		unsafePoint:    true,
		asm:            mips.AAND,
		reg: regInfo{
			inputs: []inputInfo{