V16; \ VCIPHER V17, V23, V17; \ VCIPHER V18, V23, V18; \ VCIPHER V19, V23, V19; \ VCIPHER V20, V23, V20; \ VCIPHER V21, V23, V21; \ VCIPHER V22, V23, V22 // Load input block into V1-V4 // in big endian order and // update blk_inp by 64. #define LOAD_INPUT_BLOCK64(blk_inp) \ MOVD $16, R16; \ MOVD $32, R17; \ MOVD $48, R18; \ P8_LXVB16X(blk_inp,R0,V1); \ P8_LXVB16X(blk_inp,R16,V2); \ P8_LXVB16X(blk_inp,R17,V3); \ P8_LXVB16X(blk_inp,R18,V4); \ ADD $64, blk_inp // Load input block into V1-V8 // in big endian...