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Results 1 - 7 of 7 for LDARW (0.04 sec)

  1. src/cmd/internal/obj/arm64/anames.go

    	"LDADDALH",
    	"LDADDALW",
    	"LDADDAW",
    	"LDADDB",
    	"LDADDD",
    	"LDADDH",
    	"LDADDLB",
    	"LDADDLD",
    	"LDADDLH",
    	"LDADDLW",
    	"LDADDW",
    	"LDAR",
    	"LDARB",
    	"LDARH",
    	"LDARW",
    	"LDAXP",
    	"LDAXPW",
    	"LDAXR",
    	"LDAXRB",
    	"LDAXRH",
    	"LDAXRW",
    	"LDCLRAB",
    	"LDCLRAD",
    	"LDCLRAH",
    	"LDCLRALB",
    	"LDCLRALD",
    	"LDCLRALH",
    	"LDCLRALW",
    	"LDCLRAW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 18 01:40:37 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	HVC $61428                                 // 82fe1dd4
    	ISB $1                                     // df3103d5
    	ISB $15                                    // df3f03d5
    	LDARW (R12), R29                           // 9dfddf88
    	LDARW (R30), R22                           // d6ffdf88
    	LDARW (RSP), R22                           // f6ffdf88
    	LDAR (R27), R22                            // 76ffdfc8
    	LDARB (R25), R2                            // 22ffdf08
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  3. src/internal/runtime/atomic/atomic_arm64.s

    TEXT ·Xadduintptr(SB), NOSPLIT, $0-24
    	B	·Xadd64(SB)
    
    TEXT ·Casp1(SB), NOSPLIT, $0-25
    	B ·Cas64(SB)
    
    // uint32 ·Load(uint32 volatile* addr)
    TEXT ·Load(SB),NOSPLIT,$0-12
    	MOVD	ptr+0(FP), R0
    	LDARW	(R0), R0
    	MOVW	R0, ret+8(FP)
    	RET
    
    // uint8 ·Load8(uint8 volatile* addr)
    TEXT ·Load8(SB),NOSPLIT,$0-9
    	MOVD	ptr+0(FP), R0
    	LDARB	(R0), R0
    	MOVB	R0, ret+8(FP)
    	RET
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 9K bytes
    - Viewed (0)
  4. src/runtime/sys_darwin_arm64.s

    TEXT runtime·nanotime_trampoline(SB),NOSPLIT,$40
    	MOVD	R0, R19
    	BL	libc_mach_absolute_time(SB)
    	MOVD	R0, 0(R19)
    	MOVW	timebase<>+machTimebaseInfo_numer(SB), R20
    	MOVD	$timebase<>+machTimebaseInfo_denom(SB), R21
    	LDARW	(R21), R21	// atomic read
    	CMP	$0, R21
    	BNE	initialized
    
    	SUB	$(machTimebaseInfo__size+15)/16*16, RSP
    	MOVD	RSP, R0
    	BL	libc_mach_timebase_info(SB)
    	MOVW	machTimebaseInfo_numer(RSP), R20
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Aug 03 16:07:59 UTC 2023
    - 18.3K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "LDAR", argLength: 2, reg: gpload, asm: "LDAR", faultOnNilArg0: true},
    		{name: "LDARB", argLength: 2, reg: gpload, asm: "LDARB", faultOnNilArg0: true},
    		{name: "LDARW", argLength: 2, reg: gpload, asm: "LDARW", faultOnNilArg0: true},
    
    		// atomic stores.
    		// store arg1 to arg0. arg2=mem. returns memory. auxint must be zero.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    (JumpTable idx) => (JUMPTABLE {makeJumpTableSym(b)} idx (MOVDaddr <typ.Uintptr> {makeJumpTableSym(b)} (SB)))
    
    // atomic intrinsics
    // Note: these ops do not accept offset.
    (AtomicLoad8   ...) => (LDARB ...)
    (AtomicLoad32  ...) => (LDARW ...)
    (AtomicLoad64  ...) => (LDAR  ...)
    (AtomicLoadPtr ...) => (LDAR  ...)
    
    (AtomicStore8       ...) => (STLRB ...)
    (AtomicStore32      ...) => (STLRW ...)
    (AtomicStore64      ...) => (STLR  ...)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/opGen.go

    			},
    			outputs: []outputInfo{
    				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
    			},
    		},
    	},
    	{
    		name:           "LDARW",
    		argLen:         2,
    		faultOnNilArg0: true,
    		asm:            arm64.ALDARW,
    		reg: regInfo{
    			inputs: []inputInfo{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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