// LD3 <Vt>.D[<index_1>], [<Xn|SP>]
	{0xbffffc00, 0x0d40a400, LD3, instArgs{arg_Vt_3_arrangement_D_index__Q_1, arg_Xns_mem_offset}, nil},
	// LD3 <Vt>.B[<index>], [<Xn|SP>], #3
	{0xbfffe000, 0x0ddf2000, LD3, instArgs{arg_Vt_3_arrangement_B_index__Q_S_size_1, arg_Xns_mem_post_fixedimm_3}, nil},
	// LD3 <Vt>.B[<index>], [<Xn|SP>], #<Xm>

{"Name":"LD3 (multiple structures)","Bits":"0|Q|0|0|1|1|0|0|1|1|0|Rm:5|0|1|0|0|size:2|Rn:5|Rt:5","Arch":"Post-index Register offset variant","Syntax":"LD3 { <Vt>.<T>, <Vt2>.<T>, <Vt3>.<T> }, [<Xn|SP>], <Xm>","Code":"","Alias":""},
{"Name":"LD3 (single structure)","Bits":"0|Q|0|0|1|1|0|1|0|1|0|0|0|0|0|0|001:3|S|size:2|Rn:5|Rt:5","Arch":"No offset 8-bit variant","Syntax":"LD3 { <Vt>.B, <Vt2>.B, <Vt3>.B }[<index>], [<Xn|SP>]","Code":"","Alias":""},