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Results 1 - 9 of 9 for Intel (0.13 sec)

  1. src/test/java/org/codelibs/fess/helper/UserAgentHelperTest.java

            assertEquals(UserAgentType.FIREFOX, userAgentHelper.getUserAgentType());
        }
    
        public void test_getUserAgentType_Safari() {
            getMockRequest().addHeader("user-agent",
                    "Mozilla/5.0 (Macintosh; Intel Mac OS X 10_10_5) AppleWebKit/600.8.9 (KHTML, like Gecko) Version/8.0.8 Safari/600.8.9");
            assertEquals(UserAgentType.SAFARI, userAgentHelper.getUserAgentType());
        }
    
        public void test_getUserAgentType_Opera() {
    Registered: Thu Oct 31 13:40:30 UTC 2024
    - Last Modified: Thu Feb 22 01:37:57 UTC 2024
    - 3K bytes
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  2. src/cmd/asm/internal/asm/testdata/amd64.s

    	PINSRW	$4, foo+4(SB), X2
    
    // LTYPERT spec10	{ outcode($1, &$2); }
    	JCS	2(PC)
    	RETFL	$4
    
    // Was bug: LOOP is a branch instruction.
    	JCS	2(PC)
    loop:
    	LOOP	loop // LOOP
    
    	// Intel pseudonyms for our own renamings.
    	PADDD	M2, M1 // PADDL M2, M1
    	MOVDQ2Q	X1, M1 // MOVQ X1, M1
    	MOVNTDQ	X1, (AX)	// MOVNTO X1, (AX)
    	MOVOA	(AX), X1	// MOVO (AX), X1
    
    // Tests for SP indexed addresses.
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Apr 09 18:57:21 UTC 2019
    - 3.3K bytes
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  3. guava/src/com/google/common/hash/Fingerprint2011.java

    import com.google.common.annotations.VisibleForTesting;
    
    /**
     * Implementation of Geoff Pike's fingerprint2011 hash function. See {@link Hashing#fingerprint2011}
     * for information on the behaviour of the algorithm.
     *
     * <p>On Intel Core2 2.66, on 1000 bytes, fingerprint2011 takes 0.9 microseconds compared to
     * fingerprint at 4.0 microseconds and md5 at 4.5 microseconds.
     *
    Registered: Fri Nov 01 12:43:10 UTC 2024
    - Last Modified: Tue Dec 28 17:50:25 UTC 2021
    - 6.5K bytes
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  4. README.md

    ## GNU/Linux
    
    Use the following command to run a standalone MinIO server on Linux hosts running 64-bit Intel/AMD architectures. Replace ``/data`` with the path to the drive or directory in which you want MinIO to store data.
    
    ```sh
    wget https://dl.min.io/server/minio/release/linux-amd64/minio
    chmod +x minio
    ./minio server /data
    Registered: Sun Nov 03 19:28:11 UTC 2024
    - Last Modified: Sun Oct 13 13:34:11 UTC 2024
    - 18.2K bytes
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  5. doc/asm.html

    </p>
    
    <p>
    Here follow some descriptions of key Go-specific details for the supported architectures.
    </p>
    
    <h3 id="x86">32-bit Intel 386</h3>
    
    <p>
    The runtime pointer to the <code>g</code> structure is maintained
    through the value of an otherwise unused (as far as Go is concerned) register in the MMU.
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Nov 28 19:15:27 UTC 2023
    - 36.3K bytes
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  6. cmd/testdata/xl-meta-merge.zip

    tool. For application developers, see <https://min.io/docs/minio/linux/developers/minio-drivers.html> to view MinIO SDKs for supported languages. ## GNU/Linux Use the following command to run a standalone MinIO server on Linux hosts running 64-bit Intel/AMD architectures. Replace ``/data`` with the path to the drive or directory in which you want MinIO to store data. ```sh wget https://dl.min.io/server/minio/release/linux-amd64/minio chmod +x minio ./minio server /data ``` The following table lists...
    Registered: Sun Nov 03 19:28:11 UTC 2024
    - Last Modified: Fri Mar 08 17:50:48 UTC 2024
    - 30.2K bytes
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  7. RELEASE.md

                AVX512_BF16, AMX, etc.
                ([Intel Cascade Lake](https://www.intel.com/content/www/us/en/products/platforms/details/cascade-lake.html)
                and newer CPUs.)
                *   [Example performance speedups.](https://medium.com/intel-analytics-software/leverage-intel-deep-learning-optimizations-in-tensorflow-129faa80ee07)
    Registered: Tue Nov 05 12:39:12 UTC 2024
    - Last Modified: Tue Oct 22 14:33:53 UTC 2024
    - 735.3K bytes
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  8. src/cmd/asm/internal/asm/parse.go

    // For ARM, only R0 through R15 may appear.
    // For ARM64, V0 through V31 with arrangement may appear.
    //
    // For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.
    // For range of 4 elements, Intel manual uses "+3" notation, for example:
    //
    //	VP4DPWSSDS zmm1{k1}{z}, zmm2+3, m128
    //
    // Given asm line:
    //
    //	VP4DPWSSDS Z5, [Z10-Z13], (AX)
    //
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Sep 04 18:16:59 UTC 2024
    - 36.9K bytes
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  9. cmd/testdata/decryptObjectInfo.json.zst

    ":"IAAfANaeHYrztDobiutW/YIPSQBzp24Ys1GwagljW==","X-Minio-Internal-Server-Side-Encryption-Seal-Algorithm":"DAREv2-HMAC-SHA256","content-type":"application/octet-stream"}},{"Bucket":"buck1","Name":"go_113/src/cmd/vendor/golang.org/x/arch/x86/x86asm/intel.go","UserDef":{"X-Minio-Internal-Server-Side-Encryption-Iv":"fIo431+a2sybrbT7nJeTAqZohsA/y0=","X-Minio-Internal-Server-Side-Encryption-S3-Kms-Key-Id":"my-minio-key","X-Minio-Internal-Server-Side-Encryption-S3-Kms-Sealed-Key":"IAAfALN3gZwGVKtpNfOx/...
    Registered: Sun Nov 03 19:28:11 UTC 2024
    - Last Modified: Thu Oct 29 16:34:20 UTC 2020
    - 164K bytes
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