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src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VADDPD X30, X29, X10 // 6211950058d6 VADDPD X12, X11, X28 // 6241a50858e4 VADDPD X30, X11, X28 // 6201a50858e6 VADDPD X12, X29, X28 // 6241950058e4 VADDPD X30, X29, X28 // 6201950058e6 VADDPD (AX), X29, X0 // 62f195005800 VADDPD (AX), X1, X28 // 6261f5085820 VADDPD (AX), X29, X28 // 626195005820 VADDPD (AX), X29, X10 // 627195005810
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Apr 11 18:32:50 GMT 2023 - 57.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc.s
FYL2XP1 // d9f9 HADDPD (BX), X2 // 660f7c13 HADDPD (R11), X2 // 66410f7c13 HADDPD X2, X2 // 660f7cd2 HADDPD X11, X2 // 66410f7cd3 HADDPD (BX), X11 // 66440f7c1b HADDPD (R11), X11 // 66450f7c1b HADDPD X2, X11 // 66440f7cda
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Oct 08 21:38:44 GMT 2021 - 581.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips64.s
// { // outcode(int($1), &$2, 0, &$4); // } ABSD F1, F2 // LFADD freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } ADDD F1, F2 // LFADD freg ',' freg ',' freg // { // outcode(int($1), &$2, int($4.Reg), &$6); // } ADDD F1, F2, F3 // LFCMP freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } CMPEQD F1, F2 // // WORD //
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
REMU R3, R4, R5 // 7fe41b967fff19d67bff00287cbf2050 REMD R3, R4, R5 // 7fe41bd27fff19d27cbf2050 REMDU R3, R4, R5 // 7fe41b927fff19d27cbf2050 MADDHD R3,R4,R5,R6 // 10c32170 MADDHDU R3,R4,R5,R6 // 10c32171 MODUD R3, R4, R5 // 7ca41a12 MODUW R3, R4, R5 // 7ca41a16 MODSD R3, R4, R5 // 7ca41e12
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Apr 24 15:53:25 GMT 2024 - 49K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64.s
SWPLH R5, (RSP), R7 // e7836578 SWPLB R5, (R6), R7 // c7806538 SWPLB R5, (RSP), R7 // e7836538 LDADDAD R5, (R6), R7 // c700a5f8 LDADDAD R5, (RSP), R7 // e703a5f8 LDADDAW R5, (R6), R7 // c700a5b8 LDADDAW R5, (RSP), R7 // e703a5b8
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 94.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm64enc.s
//TODO FACGT F20, F16, F27 // 1beef47e //TODO VFACGT V15.S4, V25.S4, V22.S4 // 36efaf6e //TODO VFADD V21.D2, V10.D2, V21.D2 // 55d5754e FADDS F12, F2, F10 // 4a282c1e FADDD F24, F14, F12 // cc29781e //TODO VFADDP V4.D2, F13 // 8dd8707e //TODO VFADDP V30.S4, V3.S4, V11.S4 // 6bd43e6e FCCMPS LE, F17, F12, $14 // 8ed5311e
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Mon Jul 24 01:11:41 GMT 2023 - 43.9K bytes - Viewed (1) -
src/cmd/asm/internal/asm/testdata/arm.s
// } ABSF F1, F2 // LTYPEK cond frcon ',' freg // { // outcode($1, $2, &$3, 0, &$5); // } ADDD F1, F2 MOVF $0.5, F2 // MOVF $(0.5), F2 // LTYPEK cond frcon ',' LFREG ',' freg // { // outcode($1, $2, &$3, $5, &$7); // } ADDD F1, F2, F3 // LTYPEL cond freg ',' freg // { // outcode($1, $2, &$3, int32($5.Reg), &nullgen); // } CMPD F1, F2 //
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// { // outcode(int($1), &$2, 0, &$4); // } ABSD F1, F2 // LFADD freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } ADDD F1, F2 // LFADD freg ',' freg ',' freg // { // outcode(int($1), &$2, int($4.Reg), &$6); // } ADDD F1, F2, F3 // LFCMP freg ',' freg // { // outcode(int($1), &$2, 0, &$4); // } CMPEQD F1, F2 // // WORD //
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 6.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
FLD (X5), F0 // 07b00200 FLD 4(X5), F0 // 07b04200 FSD F0, (X5) // 27b00200 FSD F0, 4(X5) // 27b20200 // 12.4: Double-Precision Floating-Point Computational Instructions FADDD F1, F0, F2 // 53011002 FSUBD F1, F0, F2 // 5301100a FMULD F1, F0, F2 // 53011012 FDIVD F1, F0, F2 // 5301101a FMIND F1, F0, F2 // 5301102a FMAXD F1, F0, F2 // 5311102a
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Mar 22 04:42:21 GMT 2024 - 16.7K bytes - Viewed (1) -
src/cmd/asm/internal/asm/testdata/arm64error.s
FMOVS (F2), F0 // ERROR "illegal combination" FMOVD F0, (F1) // ERROR "illegal combination" LDADDAD R5, (R6), RSP // ERROR "illegal combination" LDADDAW R5, (R6), RSP // ERROR "illegal combination"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 08 03:28:17 GMT 2023 - 37.8K bytes - Viewed (0)