FNMADDD	F1, F2, F3, F4				// 4f82201a

	// 12.6: Double-Precision Floating-Point Classify Instruction
	FCLASSD	F0, X5					// d31200e2

	// RISC-V Bit-Manipulation ISA-extensions (1.0)
	// 1.1: Address Generation Instructions (Zba)
	ADDUW		X10, X11, X12			// 3b86a508
	ADDUW		X10, X11			// bb85a508
	SH1ADD		X11, X12, X13			// b326b620
	SH1ADD		X11, X12			// 3326b620
	SH1ADDUW	X12, X13, X14			// 3ba7c620

needs no assembler pass in the usual pipeline.
Instead, the compiler operates on a kind of semi-abstract instruction set,
and instruction selection occurs partly after code generation.
The assembler works on the semi-abstract form, so
when you see an instruction like <code>MOV</code>
what the toolchain actually generates for that operation might
not be a move instruction at all, perhaps a clear or load.

  The <code>-w</code> flag suppresses DWARF debug information generation.
  The <code>-s</code> flag suppresses symbol table generation.
  The <code>-s</code> flag also implies the <code>-w</code> flag, which can be
  negated with <code>-w=0</code>.
  That is, <code>-s</code> <code>-w=0</code> will generate a binary with DWARF
  debug information generation but without the symbol table.
</p>

<p><!-- CL 511475 -->

pkg text/scanner, type Scanner struct, IsIdentRune func(int32, int) bool

# CL 130620043 text/template: add back pointer to Nodes for better error generation, Rob Pike <******@****.***>
pkg text/template/parse, type DotNode struct, embedded NodeType
pkg text/template/parse, type NilNode struct, embedded NodeType
pkg text/template/parse, method (*BranchNode) Copy() Node