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Results 1 - 10 of 10 for FPFlagTrue (0.18 sec)

  1. src/cmd/compile/internal/ssa/_gen/LOONG64.rules

    (CondSelect <t> x y cond) => (OR (MASKEQZ <t> x cond) (MASKNEZ <t> y cond))
    
    // Optimizations
    
    // Absorb boolean tests into block
    (NE (FPFlagTrue cmp) yes no) => (FPT cmp yes no)
    (NE (FPFlagFalse cmp) yes no) => (FPF cmp yes no)
    (EQ (FPFlagTrue cmp) yes no) => (FPF cmp yes no)
    (EQ (FPFlagFalse cmp) yes no) => (FPT cmp yes no)
    (NE (XORconst [1] cmp:(SGT _ _)) yes no) => (EQ cmp yes no)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 31.8K bytes
    - Viewed (0)
  2. src/cmd/compile/internal/ssa/_gen/MIPS.rules

    (PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 2 => (LoweredPanicExtendC [kind] hi lo y mem)
    
    // Optimizations
    
    // Absorb boolean tests into block
    (NE (FPFlagTrue cmp)  yes no) => (FPT cmp yes no)
    (NE (FPFlagFalse cmp) yes no) => (FPF cmp yes no)
    (EQ (FPFlagTrue cmp)  yes no) => (FPF cmp yes no)
    (EQ (FPFlagFalse cmp) yes no) => (FPT cmp yes no)
    (NE (XORconst [1] cmp:(SGT _ _))     yes no) => (EQ cmp yes no)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 35.3K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/_gen/MIPS64.rules

    (PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem)
    
    // Optimizations
    
    // Absorb boolean tests into block
    (NE (FPFlagTrue cmp) yes no) => (FPT cmp yes no)
    (NE (FPFlagFalse cmp) yes no) => (FPF cmp yes no)
    (EQ (FPFlagTrue cmp) yes no) => (FPF cmp yes no)
    (EQ (FPFlagFalse cmp) yes no) => (FPT cmp yes no)
    (NE (XORconst [1] cmp:(SGT _ _)) yes no) => (EQ cmp yes no)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 41.9K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/rewriteMIPS.go

    		v.AddArg(v0)
    		return true
    	}
    }
    func rewriteValueMIPS_OpEq32F(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	// match: (Eq32F x y)
    	// result: (FPFlagTrue (CMPEQF x y))
    	for {
    		x := v_0
    		y := v_1
    		v.reset(OpMIPSFPFlagTrue)
    		v0 := b.NewValue0(v.Pos, OpMIPSCMPEQF, types.TypeFlags)
    		v0.AddArg2(x, y)
    		v.AddArg(v0)
    		return true
    	}
    }
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 176.6K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/rewriteLOONG64.go

    		v.AddArg2(v0, v1)
    		return true
    	}
    }
    func rewriteValueLOONG64_OpEq32F(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	// match: (Eq32F x y)
    	// result: (FPFlagTrue (CMPEQF x y))
    	for {
    		x := v_0
    		y := v_1
    		v.reset(OpLOONG64FPFlagTrue)
    		v0 := b.NewValue0(v.Pos, OpLOONG64CMPEQF, types.TypeFlags)
    		v0.AddArg2(x, y)
    		v.AddArg(v0)
    		return true
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:26:25 UTC 2023
    - 195.8K bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/_gen/MIPSOps.go

    			faultOnNilArg1: true,
    		},
    
    		// pseudo-ops
    		{name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true}, // panic if arg0 is nil.  arg1=mem.
    
    		{name: "FPFlagTrue", argLength: 1, reg: readflags},  // bool, true if FP flag is true
    		{name: "FPFlagFalse", argLength: 1, reg: readflags}, // bool, true if FP flag is false
    
    		// Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 14:43:03 UTC 2023
    - 24K bytes
    - Viewed (0)
  7. src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go

    		// pseudo-ops
    		{name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true}, // panic if arg0 is nil.  arg1=mem.
    
    		{name: "FPFlagTrue", argLength: 1, reg: readflags},  // bool, true if FP flag is true
    		{name: "FPFlagFalse", argLength: 1, reg: readflags}, // bool, true if FP flag is false
    
    		// Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 19:04:19 UTC 2023
    - 25.2K bytes
    - Viewed (0)
  8. src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go

    		// pseudo-ops
    		{name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gpg}}, nilCheck: true, faultOnNilArg0: true}, // panic if arg0 is nil.  arg1=mem.
    
    		{name: "FPFlagTrue", argLength: 1, reg: readflags},  // bool, true if FP flag is true
    		{name: "FPFlagFalse", argLength: 1, reg: readflags}, // bool, true if FP flag is false
    
    		// Scheduler ensures LoweredGetClosurePtr occurs only in entry block,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 24 03:36:31 UTC 2023
    - 25.5K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/rewriteMIPS64.go

    		v.AddArg2(v0, v1)
    		return true
    	}
    }
    func rewriteValueMIPS64_OpEq32F(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	b := v.Block
    	// match: (Eq32F x y)
    	// result: (FPFlagTrue (CMPEQF x y))
    	for {
    		x := v_0
    		y := v_1
    		v.reset(OpMIPS64FPFlagTrue)
    		v0 := b.NewValue0(v.Pos, OpMIPS64CMPEQF, types.TypeFlags)
    		v0.AddArg2(x, y)
    		v.AddArg(v0)
    		return true
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Jul 31 03:59:48 UTC 2023
    - 211.6K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/opGen.go

    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 1073741816}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 g R23 R24 R25 R26 R27 R28 R29 R31
    			},
    		},
    	},
    	{
    		name:   "FPFlagTrue",
    		argLen: 1,
    		reg: regInfo{
    			outputs: []outputInfo{
    				{0, 1071644664}, // R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R23 R24 R25 R26 R27 R28 R29 R31
    			},
    		},
    	},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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