// FCVTZS <Xd>, <Dn>, #<fbits>
	{0xffff0000, 0x9e580000, FCVTZS, instArgs{arg_Xd, arg_Dn, arg_immediate_fbits_min_1_max_64_sub_64_scale}, nil},
	// FCVTZS <Wd>, <Sn>
	{0xfffffc00, 0x1e380000, FCVTZS, instArgs{arg_Wd, arg_Sn}, nil},
	// FCVTZS <Xd>, <Sn>
	{0xfffffc00, 0x9e380000, FCVTZS, instArgs{arg_Xd, arg_Sn}, nil},
	// FCVTZS <Wd>, <Dn>
	{0xfffffc00, 0x1e780000, FCVTZS, instArgs{arg_Wd, arg_Dn}, nil},
	// FCVTZS <Xd>, <Dn>

	//TODO FCVTZS $26, F29, F19                // b3ff665f
	//TODO VFCVTZS $45, V14.D2, V18.D2         // d2fd534f
	//TODO FCVTZS F8, F7                       // 07b9a15e
	//TODO VFCVTZS V2.S2, V4.S2                // 44b8a10e
	//TODO FCVTZS $26, F7, R11                 // eb98181e
	//TODO FCVTZS $7, F4, ZR                   // 9fe4189e
	//TODO FCVTZS $28, F13, R14                // ae91581e

{"Name":"FCVTZS (scalar, fixed-point)","Bits":"1|0|0|1|1|1|1|0|01:2|0|1|1|0|0|0|scale:6|Rn:5|Rd:5","Arch":"Double-precision to 64-bit variant","Syntax":"FCVTZS <Xd>, <Dn>, #<fbits>","Code":"","Alias":""},
{"Name":"FCVTZS (scalar, integer)","Bits":"0|0|0|1|1|1|1|0|00:2|1|1|1|0|0|0|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"Single-precision to 32-bit variant","Syntax":"FCVTZS <Wd>, <Sn>","Code":"","Alias":""},

			rno := uint16(r)
			if rno >= uint16(S0) && rno <= uint16(S31) {
				op = fmt.Sprintf("%sS", op)
			} else if rno >= uint16(D0) && rno <= uint16(D31) {
				op = fmt.Sprintf("%sD", op)
			}
		}

	case FCVTZS, FCVTZU, SCVTF, UCVTF:
		if _, ok := inst.Args[2].(Imm); !ok {
			for i := 1; i >= 0; i-- {
				if r, ok := inst.Args[i].(Reg); ok {
					rno := uint16(r)
					if rno >= uint16(S0) && rno <= uint16(S31) {