if inst.Op == ISEL {
			return fmt.Sprintf("$%d", (arg - Cond0LT))
		}
		bit := [4]string{"LT", "GT", "EQ", "SO"}[(arg-Cond0LT)%4]
		if arg <= Cond0SO {
			return bit
		} else if arg > Cond0SO && arg <= Cond7SO {
			return fmt.Sprintf("CR%d%s", int(arg-Cond0LT)/4, bit)
		} else {
			return fmt.Sprintf("CR%d", int(arg-CR0))
		}
	case Imm:
		return fmt.Sprintf("$%d", arg)

	}
}

// CondReg is a bit or field in the condition register.
type CondReg int8

const (
	_ CondReg = iota
	// Condition Regster bits
	Cond0LT
	Cond0GT
	Cond0EQ
	Cond0SO
	Cond1LT
	Cond1GT
	Cond1EQ
	Cond1SO
	Cond2LT
	Cond2GT
	Cond2EQ
	Cond2SO
	Cond3LT
	Cond3GT
	Cond3EQ
	Cond3SO
	Cond4LT
	Cond4GT
	Cond4EQ
	Cond4SO
	Cond5LT

			return "" // don't show cr0 for cmp instructions
		} else if arg >= CR0 {
			return fmt.Sprintf("cr%d", int(arg-CR0))
		}
		bit := condBit[(arg-Cond0LT)%4]
		if arg <= Cond0SO {
			return bit
		}
		return fmt.Sprintf("4*cr%d+%s", int(arg-Cond0LT)/4, bit)
	case Imm:
		return fmt.Sprintf("%d", arg)
	case SpReg:
		switch int(arg) {
		case 1:
			return "xer"
		case 8: