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Results 1 - 7 of 7 for AbsOp (0.08 sec)
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tensorflow/compiler/mlir/lite/experimental/tac/hardwares/gpu_hardware.cc
return false; } return true; } }; std::unique_ptr<TargetHardwareOperation> CreateConvOp() { return std::make_unique<GpuConvOp>(); } // Op registrations TAC_REGISTER_GPU_OP(AbsOp, CreateBasicOpNoCost); TAC_REGISTER_GPU_OP(AveragePool2DOp, CreateBasicOpNoCost); TAC_REGISTER_GPU_OP(CosOp, CreateBasicOpNoCost); TAC_REGISTER_GPU_OP(DivOp, CreateBasicOpNoCost);
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 06 03:08:33 UTC 2023 - 7.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/quantization/tensorflow/fallback_to_flex_ops.cc
&QuantizableOpsInLegacyMode() { static const std::set<std::string> *legacy_op_list = new std::set<std::string>({ // clang-format off // go/keep-sorted start TF::AbsOp::getOperationName().str(), TF::AddOp::getOperationName().str(), TF::AddV2Op::getOperationName().str(), TF::ArgMaxOp::getOperationName().str(), TF::AvgPoolOp::getOperationName().str(),
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 12.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/transforms/legalization_op_config.cc
// MatrixDiagPartV3 should use the MLIR implementation due to performance. TypeID::get<TF::MatrixDiagPartV3Op>(), // Ops that are legalized in the old bridge using MlirXlaOpKernel TypeID::get<TF::AbsOp>(), TypeID::get<TF::AtanOp>(), TypeID::get<TF::AvgPool3DOp>(), TypeID::get<TF::BiasAddGradOp>(), TypeID::get<TF::CeilOp>(), TypeID::get<TF::CheckNumericsOp>(), TypeID::get<TF::CosOp>(),
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Apr 24 04:08:35 UTC 2024 - 21.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/transforms/lower_tf.cc
IsInfOp::getOperationName(), MulOp::getOperationName(), FloorOp::getOperationName(), AbsOp::getOperationName(), GreaterOp::getOperationName(), SinOp::getOperationName(), IsFiniteOp::getOperationName(), }) {}
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 74.9K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/ir/tfl_ops.cc
return op.emitError("SvdfOp expected to have one stateful operand"); } //===----------------------------------------------------------------------===// // AbsOp //===----------------------------------------------------------------------===// OpFoldResult AbsOp::fold(FoldAdaptor adaptor) { auto operands = adaptor.getOperands(); Type result_type = getType(); // Only constant fold for tensor of f32 is implemented.
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 169.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/ir/tf_ops_a_m.cc
namespace mlir { namespace TF { namespace { #include "tensorflow/compiler/mlir/tensorflow/transforms/generated_canonicalize.inc" } // namespace INFER_RETURN_TYPE_COMPONENTS_FROM_OPERANDS(AbsOp); INFER_RETURN_TYPE_COMPONENTS_FROM_OPERANDS(AcosOp); INFER_RETURN_TYPE_COMPONENTS_FROM_OPERANDS(AcoshOp); INFER_RETURN_TYPE_COMPONENTS_FROM_OPERANDS(AsinOp); INFER_RETURN_TYPE_COMPONENTS_FROM_OPERANDS(AsinhOp);
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu Apr 25 16:01:03 UTC 2024 - 146.7K bytes - Viewed (0) -
tensorflow/compiler/mlir/tf2xla/transforms/legalize_tf.cc
// // %size = ceil(abs((%limit - %start) / %delta)) auto range = rewriter.create<mhlo::SubtractOp>(op.getLoc(), limit, start); auto abs = rewriter.create<mhlo::AbsOp>(op.getLoc(), range); // Delta is not necessarily the same type as start and limit. auto abs_cast = rewriter.create<mhlo::ConvertOp>(op.getLoc(), compute_type, abs); auto delta_cast =
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 20:00:43 UTC 2024 - 291.8K bytes - Viewed (0)