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Results 1 - 3 of 3 for ASH1ADD (0.15 sec)
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src/cmd/internal/obj/riscv/cpu.go
// 4.2.1: Supervisor Memory-Management Fence Instruction ASFENCEVMA // // RISC-V Bit-Manipulation ISA-extensions (1.0) // // 1.1: Address Generation Instructions (Zba) AADDUW ASH1ADD ASH1ADDUW ASH2ADD ASH2ADDUW ASH3ADD ASH3ADDUW ASLLIUW // 1.2: Basic Bit Manipulation (Zbb) AANDN AORN AXNOR ACLZ ACLZW ACTZ ACTZW ACPOP ACPOPW
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/inst.go
case ASEXTH: return &inst{0x13, 0x1, 0x5, 1541, 0x30} case ASFENCEVMA: return &inst{0x73, 0x0, 0x0, 288, 0x9} case ASH: return &inst{0x23, 0x1, 0x0, 0, 0x0} case ASH1ADD: return &inst{0x33, 0x2, 0x0, 512, 0x10} case ASH1ADDUW: return &inst{0x3b, 0x2, 0x0, 512, 0x10} case ASH2ADD: return &inst{0x33, 0x4, 0x0, 512, 0x10} case ASH2ADDUW:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.9K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
AADDIW, ASLLIW, ASRLIW, ASRAIW, AADDW, ASUBW, ASLLW, ASRLW, ASRAW, AADD, AAND, AOR, AXOR, ASLL, ASRL, ASUB, ASRA, AMUL, AMULH, AMULHU, AMULHSU, AMULW, ADIV, ADIVU, ADIVW, ADIVUW, AREM, AREMU, AREMW, AREMUW, AADDUW, ASH1ADD, ASH1ADDUW, ASH2ADD, ASH2ADDUW, ASH3ADD, ASH3ADDUW, ASLLIUW, AANDN, AORN, AXNOR, AMAX, AMAXU, AMIN, AMINU, AROL, AROLW, AROR, ARORW, ARORI, ARORIW, ABCLR, ABCLRI, ABEXT, ABEXTI, ABINV, ABINVI, ABSET, ABSETI: p.Reg = p.To.Reg
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0)