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Results 1 - 6 of 6 for ANDLconst (0.34 sec)
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src/cmd/compile/internal/ssa/_gen/AMD64.rules
// Fold extensions and ANDs together. (MOVBQZX (ANDLconst [c] x)) => (ANDLconst [c & 0xff] x) (MOVWQZX (ANDLconst [c] x)) => (ANDLconst [c & 0xffff] x) (MOVLQZX (ANDLconst [c] x)) => (ANDLconst [c] x) (MOVBQSX (ANDLconst [c] x)) && c & 0x80 == 0 => (ANDLconst [c & 0x7f] x) (MOVWQSX (ANDLconst [c] x)) && c & 0x8000 == 0 => (ANDLconst [c & 0x7fff] x) (MOVLQSX (ANDLconst [c] x)) && uint32(c) & 0x80000000 == 0 => (ANDLconst [c & 0x7fffffff] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewrite386.go
v_0 := v.Args[0] // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != Op386ANDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0] v.reset(Op386ANDLconst) v.AuxInt = int32ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDLconst [c] _) // cond: c==0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Apr 21 21:05:46 UTC 2023 - 262.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteAMD64.go
v.AddArg(v0) return true } break } return false } func rewriteValueAMD64_OpAMD64ANDLconst(v *Value) bool { v_0 := v.Args[0] // match: (ANDLconst [c] (ANDLconst [d] x)) // result: (ANDLconst [c & d] x) for { c := auxIntToInt32(v.AuxInt) if v_0.Op != OpAMD64ANDLconst { break } d := auxIntToInt32(v_0.AuxInt) x := v_0.Args[0]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 712.7K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/386Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 14 08:10:32 UTC 2023 - 45.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 04 16:40:24 UTC 2023 - 98K bytes - Viewed (1) -
src/cmd/compile/internal/ssa/opGen.go
{0, 239}, // AX CX DX BX BP SI DI {1, 239}, // AX CX DX BX BP SI DI }, outputs: []outputInfo{ {0, 239}, // AX CX DX BX BP SI DI }, }, }, { name: "ANDLconst", auxType: auxInt32, argLen: 1, resultInArg0: true, clobberFlags: true, asm: x86.AANDL, reg: regInfo{ inputs: []inputInfo{ {0, 239}, // AX CX DX BX BP SI DI
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)