AFCVTLUS
	AFCVTSWU
	AFCVTSLU
	AFSGNJS
	AFSGNJNS
	AFSGNJXS
	AFMVXS
	AFMVSX
	AFMVXW
	AFMVWX

	// 11.8: Single-Precision Floating-Point Compare Instructions
	AFEQS
	AFLTS
	AFLES

	// 11.9: Single-Precision Floating-Point Classify Instruction
	AFCLASSS

	// 12.3: Double-Precision Load and Store Instructions
	AFLD
	AFSD

	case AFLD:
		return &inst{0x7, 0x3, 0x0, 0, 0x0}
	case AFLED:
		return &inst{0x53, 0x0, 0x0, -1504, 0x51}
	case AFLEQ:
		return &inst{0x53, 0x0, 0x0, -1440, 0x53}
	case AFLES:
		return &inst{0x53, 0x0, 0x0, -1536, 0x50}
	case AFLQ:
		return &inst{0x7, 0x4, 0x0, 0, 0x0}
	case AFLTD:
		return &inst{0x53, 0x1, 0x0, -1504, 0x51}
	case AFLTQ:
		return &inst{0x53, 0x1, 0x0, -1440, 0x53}

	AFMVXW & obj.AMask:   rFIEncoding,
	AFMVWX & obj.AMask:   rIFEncoding,

	// 11.8: Single-Precision Floating-Point Compare Instructions
	AFEQS & obj.AMask: rFFIEncoding,
	AFLTS & obj.AMask: rFFIEncoding,
	AFLES & obj.AMask: rFFIEncoding,

	// 11.9: Single-Precision Floating-Point Classify Instruction
	AFCLASSS & obj.AMask: rFIEncoding,

	// 12.3: Double-Precision Load and Store Instructions

				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
			},
		},
	},
	{
		name:   "FLES",
		argLen: 2,
		asm:    riscv.AFLES,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31