// 1.3: Bitwise Rotation (Zbb)
	AROL
	AROLW
	AROR
	ARORI
	ARORIW
	ARORW
	AORCB
	AREV8

	// 1.5: Single-bit Instructions (Zbs)
	ABCLR
	ABCLRI
	ABEXT
	ABEXTI
	ABINV
	ABINVI
	ABSET
	ABSETI

	// The escape hatch. Inserts a single 32-bit word.
	AWORD

	// Pseudo-instructions.  These get translated by the assembler into other
	// instructions, based on their operands.

		return &inst{0x33, 0x5, 0x0, 1152, 0x24}
	case ABEXTI:
		return &inst{0x13, 0x5, 0x0, 1152, 0x24}
	case ABGE:
		return &inst{0x63, 0x5, 0x0, 0, 0x0}
	case ABGEU:
		return &inst{0x63, 0x7, 0x0, 0, 0x0}
	case ABINV:
		return &inst{0x33, 0x1, 0x0, 1664, 0x34}
	case ABINVI:
		return &inst{0x13, 0x1, 0x0, 1664, 0x34}
	case ABLT:
		return &inst{0x63, 0x4, 0x0, 0, 0x0}
	case ABLTU:
		return &inst{0x63, 0x6, 0x0, 0, 0x0}

			AREM, AREMU, AREMW, AREMUW,
			AADDUW, ASH1ADD, ASH1ADDUW, ASH2ADD, ASH2ADDUW, ASH3ADD, ASH3ADDUW, ASLLIUW,
			AANDN, AORN, AXNOR, AMAX, AMAXU, AMIN, AMINU, AROL, AROLW, AROR, ARORW, ARORI, ARORIW,
			ABCLR, ABCLRI, ABEXT, ABEXTI, ABINV, ABINVI, ABSET, ABSETI:
			p.Reg = p.To.Reg
		}
	}

	// Rewrite instructions with constant operands to refer to the immediate
	// form of the instruction.
	if p.From.Type == obj.TYPE_CONST {
		switch p.As {