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Results 1 - 4 of 4 for AANDI (0.11 sec)
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src/cmd/internal/obj/riscv/cpu.go
const ( // Unprivileged ISA (Document Version 20190608-Base-Ratified) // 2.4: Integer Computational Instructions AADDI = obj.ABaseRISCV + obj.A_ARCHSPECIFIC + iota ASLTI ASLTIU AANDI AORI AXORI ASLLI ASRLI ASRAI ALUI AAUIPC AADD ASLT ASLTU AAND AOR AXOR ASLL ASRL ASUB ASRA // 2.5: Control Transfer Instructions
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.1K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
func progedit(ctxt *obj.Link, p *obj.Prog, newprog obj.ProgAlloc) { // Expand binary instructions to ternary ones. if p.Reg == obj.REG_NONE { switch p.As { case AADDI, ASLTI, ASLTIU, AANDI, AORI, AXORI, ASLLI, ASRLI, ASRAI, AADDIW, ASLLIW, ASRLIW, ASRAIW, AADDW, ASUBW, ASLLW, ASRLW, ASRAW, AADD, AAND, AOR, AXOR, ASLL, ASRL, ASUB, ASRA, AMUL, AMULH, AMULHU, AMULHSU, AMULW, ADIV, ADIVU, ADIVW, ADIVUW,
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/inst.go
return &inst{0x2f, 0x2, 0x0, 128, 0x4} case AAMOXORD: return &inst{0x2f, 0x3, 0x0, 512, 0x10} case AAMOXORW: return &inst{0x2f, 0x2, 0x0, 512, 0x10} case AAND: return &inst{0x33, 0x7, 0x0, 0, 0x0} case AANDI: return &inst{0x13, 0x7, 0x0, 0, 0x0} case AANDN: return &inst{0x33, 0x7, 0x0, 1024, 0x20} case AAUIPC: return &inst{0x17, 0x0, 0x0, 0, 0x0} case ABCLR: return &inst{0x33, 0x1, 0x0, 1152, 0x24}
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Mar 20 14:19:33 UTC 2024 - 13.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, }, }, { name: "ANDI", auxType: auxInt64, argLen: 1, asm: riscv.AANDI, reg: regInfo{ inputs: []inputInfo{ {0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 }, outputs: []outputInfo{
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)