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Results 1 - 4 of 4 for 1x28x28x64xf16 (0.12 sec)

  2. github.com/tensorflow/tensorflow

    tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_gpu_cc_60.mlir 

             strides = [1, 1, 1, 1]
       } : (tensor<4xi32>, tensor<1x28x28x64xf16>, tensor<1x28x28x64xf16>)
        -> tensor<1x28x28x64xf16>

  func.return %0 : tensor<1x28x28x64xf16>
}

// CHECK-LABEL: func @transposeFusedBatchNormV3_f32
func.func @transposeFusedBatchNormV3_f32(
  %arg0: tensor<1x28x28x64xf32>,
  %arg1: tensor<64xf32>
) -> tensor<1x28x28x64xf32> {

  // CHECK: "tf.FusedBatchNormV3"
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 21 08:41:18 UTC 2022
    - 5.8K bytes
    - Viewed (0)
  3. github.com/tensorflow/tensorflow

    tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_gpu_cc_70.mlir 

             padding = "VALID",
         strides = [1, 1, 1, 1]
       } : (tensor<4xi32>, tensor<1x28x28x64xf32>, tensor<1x28x28x64xf32>)
        -> tensor<1x28x28x64xf32>

  func.return %0 : tensor<1x28x28x64xf32>
}

// CHECK-LABEL: func @transposeConv2DBackpropInput_f16
func.func @transposeConv2DBackpropInput_f16(
  %input_size:   tensor<4xi32>,
  %filter:       tensor<1x64x28x28xf16>,
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Tue Jun 21 08:41:18 UTC 2022
    - 8.5K bytes
    - Viewed (0)
  4. github.com/tensorflow/tensorflow

    tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nchw.mlir 

             is_training = true
       }
        : (tensor<1x28x28x64xf32>, tensor<1x28x28x64xf32>,
           tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>)
       -> (tensor<1x28x28x64xf32>,
           tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>)

  func.return %x_backprop : tensor<1x28x28x64xf32>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 9K bytes
    - Viewed (0)
  5. github.com/tensorflow/tensorflow

    tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nhwc.mlir 

      // CHECK: "tf.FusedBatchNormV3"
  // CHECK-SAME: (%[[ARG_TRANSPOSE]], %arg1, %arg1, %arg1, %arg1)
  // CHECK-SAME: data_format = "NHWC"
  // CHECK-SAME: (tensor<1x28x28x64xf32>, tensor<64xf32>,
  // CHECK-SAME: -> (tensor<1x28x28x64xf32>, tensor<64xf32>,

  // CHECK: %[[RES_PERM:.*]] = "tf.Const"()
  // CHECK-SAME: <{value = dense<[0, 3, 1, 2]> : tensor<4xi64>}>
    Registered: Sun Jun 16 05:45:23 UTC 2024
    - Last Modified: Mon Oct 30 06:52:55 UTC 2023
    - 4.5K bytes
    - Viewed (0)
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