VBROADCASTF32X4 -7(DI), K2, Z16                    // 62e27d4a1a87f9ffffff
	VBROADCASTF64X4 15(R8)(R14*1), K1, Z3              // 6292fd491b9c300f000000
	VBROADCASTF64X4 15(R8)(R14*2), K1, Z3              // 6292fd491b9c700f000000
	VBROADCASTF64X4 15(R8)(R14*1), K1, Z12             // 6212fd491ba4300f000000
	VBROADCASTF64X4 15(R8)(R14*2), K1, Z12             // 6212fd491ba4700f000000

	VPOPCNTD -15(R14)(R15*1), K5, Y26                  // 62027d2d55943ef1ffffff
	VPOPCNTD -15(BX), K5, Y26                          // 62627d2d5593f1ffffff
	VPOPCNTD Y22, K5, Y30                              // 62227d2d55f6
	VPOPCNTD Y3, K5, Y30                               // 62627d2d55f3
	VPOPCNTD Y15, K5, Y30                              // 62427d2d55f7

pkg syscall (freebsd-386), const DLT_IEEE802_11_RADIO_AVS = 163
pkg syscall (freebsd-386), const DLT_IEEE802_15_4 = 195
pkg syscall (freebsd-386), const DLT_IEEE802_15_4_LINUX = 191
pkg syscall (freebsd-386), const DLT_IEEE802_15_4_NOFCS = 230
pkg syscall (freebsd-386), const DLT_IEEE802_15_4_NOFCS ideal-int
pkg syscall (freebsd-386), const DLT_IEEE802_15_4_NONASK_PHY = 215
pkg syscall (freebsd-386), const DLT_IEEE802_16_MAC_CPS = 188

	VPMADD52HUQ 15(DX)(BX*2), Y31, K7, Y17             // 62e28527b58c5a0f000000
	VPMADD52HUQ Y28, Y8, K7, Y17                       // 6282bd2fb5cc
	VPMADD52HUQ Y13, Y8, K7, Y17                       // 62c2bd2fb5cd
	VPMADD52HUQ Y7, Y8, K7, Y17                        // 62e2bd2fb5cf
	VPMADD52HUQ (R8), Y8, K7, Y17                      // 62c2bd2fb508
	VPMADD52HUQ 15(DX)(BX*2), Y8, K7, Y17              // 62e2bd2fb58c5a0f000000

	VP4DPWSSD 15(DX)(BX*8), [Z2-Z5], K4, Z17           // 62e26f4c528cda0f000000
	VP4DPWSSD 7(SI)(DI*1), [Z12-Z15], K4, Z17          // 62e21f4c528c3e07000000
	VP4DPWSSD 15(DX)(BX*8), [Z12-Z15], K4, Z17         // 62e21f4c528cda0f000000
	VP4DPWSSD 7(SI)(DI*1), [Z22-Z25], K4, Z17          // 62e24f44528c3e07000000
	VP4DPWSSD 15(DX)(BX*8), [Z22-Z25], K4, Z17         // 62e24f44528cda0f000000

	VPCLMULQDQ $97, 15(DX)(BX*8), Z26, Z24             // 62632d404484da0f00000061 or 6263ad404484da0f00000061
	VPCLMULQDQ $97, Z9, Z0, Z12                        // 62537d4844e161 or 6253fd4844e161
	VPCLMULQDQ $97, Z3, Z0, Z12                        // 62737d4844e361 or 6273fd4844e361
	VPCLMULQDQ $97, 7(SI)(DI*1), Z0, Z12               // 62737d4844a43e0700000061 or 6273fd4844a43e0700000061

	VPERMI2B 15(R8)(R14*1), Y15, K2, Y2                // 6292052a7594300f000000
	VPERMI2B 15(R8)(R14*2), Y15, K2, Y2                // 6292052a7594700f000000
	VPERMI2B Y18, Y22, K2, Y2                          // 62b24d2275d2
	VPERMI2B Y24, Y22, K2, Y2                          // 62924d2275d0
	VPERMI2B Y9, Y22, K2, Y2                           // 62d24d2275d1

			p.errorf("rhs of shift must be integer: %s", str)
		} else {
			r2, ok := p.registerReference(str)
			if !ok {
				p.errorf("rhs of shift must be register or integer: %s", str)
			}
			count = (r2&15)<<8 | 1<<4
		}
	case scanner.Int, '(':
		p.back()
		x := int64(p.expr())
		if p.arch.Family == sys.ARM64 {
			if x >= 64 {
				p.errorf("register shift count too large: %s", str)
			}

	RLDCRCC $0, R4, $-16, R6        // 788606f3
	RLDICL $0, R4, $15, R6          // 788603c0
	RLDICLCC $0, R4, $15, R6        // 788603c1
	RLDICR $0, R4, $15, R6          // 788603c4
	RLDICRCC $0, R4, $15, R6        // 788603c5
	RLDIC $0, R4, $15, R6           // 788603c8
	RLDICCC $0, R4, $15, R6         // 788603c9
	CLRLSLWI $16, R5, $8, R4        // 54a4422e
	CLRLSLDI $24, R4, $2, R3        // 78831588
	RLDCR	$1, R1, $-16, R1        // 78210ee4

	VADDPD 15(CX)(AX*1), Y10, Y29   // 6261ad2858ac010f000000
	VADDPD 15(CX)(AX*1), Y28, Y10   // 62719d205894010f000000
	VADDPD 15(CX)(AX*2), Y0, Y29    // 6261fd2858ac410f000000
	VADDPD 15(CX)(AX*2), Y28, Y1    // 62f19d20588c410f000000
	VADDPD 15(CX)(AX*2), Y28, Y29   // 62619d2058ac410f000000
	VADDPD 15(CX)(AX*2), Y10, Y29   // 6261ad2858ac410f000000
	VADDPD 15(CX)(AX*2), Y28, Y10   // 62719d205894410f000000