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src/cmd/asm/internal/asm/testdata/riscv64.s
CSRRC X0, CYCLE, X0 // 733000c0 CSRRC X10, CYCLE, X5 // f33205c0 CSRRC $2, TIME, X5 // f37211c0 CSRRCI $2, TIME, X5 // f37211c0 CSRRS X0, CYCLE, X5 // f32200c0 CSRRS X0, CYCLE, X0 // 732000c0 CSRRS X10, CYCLE, X5 // f32205c0 CSRRS $2, TIME, X5 // f36211c0 CSRRS X0, VLENB, X5 // f32220c2 CSRRSI $2, TIME, X5 // f36211c0 CSRRW X0, CYCLE, X5 // f31200c0 CSRRW X0, CYCLE, X0 // 731000c0
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Sat Apr 04 05:25:40 GMT 2026 - 74.2K bytes - Click Count (0) -
docs/en/docs/release-notes.md
* 📝 Add note about `time.perf_counter()` in middlewares. PR [#12095](https://github.com/fastapi/fastapi/pull/12095) by [@tiangolo](https://github.com/tiangolo). * 📝 Tweak middleware code sample `time.time()` to `time.perf_counter()`. PR [#11957](https://github.com/fastapi/fastapi/pull/11957) by [@domdent](https://github.com/domdent).
Created: Sun Apr 05 07:19:11 GMT 2026 - Last Modified: Fri Apr 03 12:07:04 GMT 2026 - 631K bytes - Click Count (0)