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src/cmd/asm/internal/asm/testdata/riscv64.s
CSRRW X0, CYCLE, X5 // f31200c0 CSRRW X0, CYCLE, X0 // 731000c0 CSRRW X10, CYCLE, X5 // f31205c0 CSRRW $2, TIME, X5 // f35211c0 CSRRWI $2, TIME, X5 // f35211c0 // 8.1: Base Counters and Timers (Zicntr) RDCYCLE X5 // f32200c0 RDTIME X5 // f32210c0 RDINSTRET X5 // f32220c0 // 10.1: Zihintpause Extension for Pause Hint PAUSE // 0f000001
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Sat Apr 04 05:25:40 GMT 2026 - 74.2K bytes - Click Count (0)