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src/cmd/asm/internal/asm/testdata/riscv64.s
SH X5, (X6) // 23105300 SH X5, 4(X6) // 23125300 SB X5, (X6) // 23005300 SB X5, 4(X6) // 23025300 // 2.7: Memory Ordering Instructions FENCE // 0f00f00f FENCE W, W // 0f001001 FENCE I, O // 0f004008 FENCE IORW, IORW // 0f00f00f FENCE.TSO // 0f003083 // 4.2: Integer Computational Instructions (RV64I) ADDIW $1, X5, X6 // 1b831200 SLLIW $1, X5, X6 // 1b931200
Created: Tue Apr 07 11:13:11 GMT 2026 - Last Modified: Sat Apr 04 05:25:40 GMT 2026 - 74.2K bytes - Click Count (0)