STP.W	(R3, R4), 8(RSP)    // e39380a9
	STP.P	(R3, R4), 8(RSP)    // e39380a8
	STP	(R3, R4), -8(RSP)   // e3933fa9
	STP	(R3, R4), 11(RSP)   // fb2f0091631300a9
	STP	(R3, R4), 1024(RSP) // fb031091631300a9
	STP	(R3, R4), x(SB)
	STP	(R3, R4), x+8(SB)
	STPW	(R3, R4), (R5)      // a3100029
	STPW	(R3, R4), 4(R5)     // a3900029
	STPW.W	(R3, R4), 4(R5)     // a3908029
	STPW.P	(R3, R4), 4(R5)     // a3908028

        MavenArtifactRepositorySubclass r3 = new MavenArtifactRepositorySubclass("bar");

        assertTrue(r1.hashCode() == r2.hashCode());
        assertFalse(r1.hashCode() == r3.hashCode());

        assertTrue(r1.equals(r2), "Expected " + r1 + " to equal " + r2);
        assertTrue(r2.equals(r1), "Expected " + r2 + " to equal " + r1);

        assertFalse(r1.equals(r3), "Expected " + r1 + " to not equal " + r3);

	CINC	CS, R2, R3, R4                                   // ERROR "illegal combination"
	CSEL	LT, R1, R2                                       // ERROR "illegal combination"
	CINC	AL, R2, R3                                       // ERROR "invalid condition"
	CINC	NV, R2, R3                                       // ERROR "invalid condition"
	CINVW	AL, R2, R3                                       // ERROR "invalid condition"

+ a1×b1 + a2×b0 + 19×(a3×b4 + a4×b3) r2 := mul64(a0, b2) r2 = addMul64(r2, a1, b1) r2 = addMul64(r2, a2, b0) r2 = addMul64(r2, a3_19, b4) r2 = addMul64(r2, a4_19, b3) // r3 = a0×b3 + a1×b2 + a2×b1 + a3×b0 + 19×a4×b4 r3 := mul64(a0, b3) r3 = addMul64(r3, a1, b2) r3 = addMul64(r3, a2, b1) r3 = addMul64(r3, a3, b0) r3 = addMul64(r3, a4_19, b4) // r4 = a0×b4 + a1×b3 + a2×b2 + a3×b1 + a4×b0 r4 := mul64(a0, b4) r4 = addMul64(r4, a1, b3) r4 = addMul64(r4, a2, b2) r4 = addMul64(r4, a3, b1) r4 = addMul64(r4,...

b2) // r2 = a0×b2 + a1×b1 + a2×b0 + 19×(a3×b4 + a4×b3) r2 := mul(a0, b2) r2 = addMul(r2, a1, b1) r2 = addMul(r2, a2, b0) r2 = addMul19(r2, a3, b4) r2 = addMul19(r2, a4, b3) // r3 = a0×b3 + a1×b2 + a2×b1 + a3×b0 + 19×a4×b4 r3 := mul(a0, b3) r3 = addMul(r3, a1, b2) r3 = addMul(r3, a2, b1) r3 = addMul(r3, a3, b0) r3 = addMul19(r3, a4, b4) // r4 = a0×b4 + a1×b3 + a2×b2 + a3×b1 + a4×b0 r4 := mul(a0, b4) r4 = addMul(r4, a1, b3) r4 = addMul(r4, a2, b2) r4 = addMul(r4, a3, b1) r4 = addMul(r4, a4, b0) // After...

		}
		// fmt.Printf("SYM %s\n", obj.Dconv(&emptyProg, 0, a))
		if p.peek() == scanner.EOF {
			return
		}
	}

	// Special register list syntax for arm: [R1,R3-R7]
	if tok.ScanToken == '[' {
		if prefix != 0 {
			p.errorf("illegal use of register list")
		}
		p.registerList(a)
		p.expectOperandEnd()
		return
	}

	// Register: R1