def op2 = operations.first(ResolveConfigurationDependenciesBuildOperationType)
        op2.details.repositories.size() == 2
        op2.details.repositories*.id.unique(false).size() == 2
        op2.details.repositories[0].name == 'withoutCreds'
        op2.details.repositories[1].name == 'withCreds'
        def repo2Id = op2.details.repositories[0].id

// Specify this trait if the bias-th input of the op is a bias input, which
// needs a scale based on the scales of op1 and op2.
class AccumulatorUniformScale<int bias, int op1, int op2> : NativeOpTrait<
  !strconcat("quant::AccumulatorUniformScale<",
             !interleave([bias, op1, op2], ", "),
             ">::Impl")>;

// Specify the operand index of the coefficient operand for an affine op

  if (argc != 4) {
    for (int i = 1; i < argc; ++i) {
      fprintf(stderr, "Arg %d = %s\n", i, argv[i]);
    }
    fprintf(stderr, "Usage: %s location api_def1,api_def2 op1,op2,op3\n",
            argv[0]);
    exit(1);
  }
  for (int i = 1; i < argc; ++i) {
    fprintf(stdout, "Arg %d = %s\n", i, argv[i]);
  }
  std::vector<tensorflow::string> api_def_srcs = tensorflow::str_util::Split(

// Wrap op result uses in an unrealized cast to create a cast to buffer
// any type changes to result, and apply type converter to result:
//   result = op(V0)
//   V1     = op2(result)
//   ==>
//   result = op(V0)
//   V1     = unrealized_cast(result)
//   V2     = op2(V1)
void ConvertAndWrapUsesInUnrealizedCast(Value result, TypeConverter &converter,
                                        IRRewriter &rewriter) {

(Store {t1} op1:(OffPtr [o1] p1) d1
	m2:(Store {t2} op2:(OffPtr [0] p2) d2
		m3:(Move [n] p3 _ mem)))
	&& m2.Uses == 1 && m3.Uses == 1
	&& o1 == t2.Size()
	&& n == t2.Size() + t1.Size()
	&& isSamePtr(p1, p2) && isSamePtr(p2, p3)
	&& clobber(m2, m3)
	=> (Store {t1} op1 d1 (Store {t2} op2 d2 mem))
(Store {t1} op1:(OffPtr [o1] p1) d1
	m2:(Store {t2} op2:(OffPtr [o2] p2) d2
		m3:(Store {t3} op3:(OffPtr [0] p3) d3

		p1 := v_1
		mem := v_2
		if mem.Op != OpStore {
			break
		}
		t2 := auxToType(mem.Aux)
		_ = mem.Args[2]
		op2 := mem.Args[0]
		if op2.Op != OpOffPtr {
			break
		}
		tt2 := op2.Type
		o2 := auxIntToInt64(op2.AuxInt)
		p2 := op2.Args[0]
		d1 := mem.Args[1]
		mem_2 := mem.Args[2]
		if mem_2.Op != OpStore {
			break
		}
		t3 := auxToType(mem_2.Aux)

  SmallVector<func::FuncOp> func_ops(iterator_range.begin(),
                                     iterator_range.end());
  absl::c_sort(func_ops, [](func::FuncOp op1, func::FuncOp op2) {
    return op1.getName() < op2.getName();
  });
  return func_ops;
}

	return n
}

/* form offset parameter to SYS; special register number */
func SYSARG5(op0 int, op1 int, Cn int, Cm int, op2 int) int {
	return op0<<19 | op1<<16 | Cn<<12 | Cm<<8 | op2<<5
}

func SYSARG4(op1 int, Cn int, Cm int, op2 int) int {
	return SYSARG5(0, op1, Cn, Cm, op2)
}

// checkUnpredictable checks if the source and transfer registers are the same register.

  const auto& op1 = subgraph->operators[1].get();
  const auto& op2 = subgraph->operators[2].get();
  const auto& op3 = subgraph->operators[3].get();
  const auto& op4 = subgraph->operators[4].get();

  ASSERT_THAT(GetBuiltinCode(model_.operator_codes[op1->opcode_index].get()),
              Eq(BuiltinOperator_QUANTIZE));
  ASSERT_THAT(GetBuiltinCode(model_.operator_codes[op2->opcode_index].get()),
              Eq(BuiltinOperator_QUANTIZE));

		}
		op1, op2, it := conv.op1, conv.op2, conv.intermediateType

		if op1 != ssa.OpInvalid && op2 != ssa.OpInvalid {
			// normal case, not tripping over unsigned 64
			if op1 == ssa.OpCopy {
				if op2 == ssa.OpCopy {
					return v
				}
				return s.newValueOrSfCall1(op2, tt, v)
			}
			if op2 == ssa.OpCopy {
				return s.newValueOrSfCall1(op1, tt, v)
			}