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Results 1 - 10 of 826 for nRules (0.11 sec)
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internal/event/rules.go
rulesCopy[pattern] = targetIDSet.Clone() } return rulesCopy } // Union - returns union with given rules as new rules. func (rules Rules) Union(rules2 Rules) Rules { nrules := rules.Clone() for pattern, targetIDSet := range rules2 { nrules[pattern] = nrules[pattern].Union(targetIDSet) } return nrules } // Difference - returns difference with given rules as new rules.
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Fri May 24 23:05:23 UTC 2024 - 2.7K bytes - Viewed (0) -
cmd/site-replication.go
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Fri May 24 23:05:23 UTC 2024 - 184.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64latelower.rules
// Copyright 2022 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // This file contains rules used by the laterLower pass. // These are often the exact inverse of rules in ARM64.rules. (ADDconst [c] x) && !isARM64addcon(c) => (ADD x (MOVDconst [c])) (SUBconst [c] x) && !isARM64addcon(c) => (SUB x (MOVDconst [c]))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 4.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules
// Copyright 2022 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. // This file contains rules used by the laterLower pass. // Simplify ISEL x $0 z into ISELZ (ISEL [a] x (MOVDconst [0]) z) => (ISELZ [a] x z) // Simplify ISEL $0 y z into ISELZ by inverting comparison and reversing arguments. (ISEL [a] (MOVDconst [0]) y z) => (ISELZ [a^0x4] y z)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 3.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64latelower.rules
the shift input. L6:(SAR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SARX(Q|L) x y) L7:(SHL(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHLX(Q|L) x y) L8:(SHR(Q|L) x y) && buildcfg.GOAMD64 >= 3 => (SHRX(Q|L) x y) L9: L10:// See comments in ARM64latelower.rules for why these are here. L11:(MOVLQZX x) && zeroUpper32Bits(x,3) => x L12:(MOVWQZX x) && zeroUpper48Bits(x,3) => x L13:(MOVBQZX x) && zeroUpper56Bits(x,3) => x ...
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 636 bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/generic.rules
// Go source code // // y := 0 * x // // can be translated into y := 0 without losing any information, which saves a // pointless multiplication instruction. Other .rules files in this directory // (for example AMD64.rules) contain rules specific to the architecture in the // filename. The rules here apply to every architecture. // // The code for parsing this file lives in rulegen.go; this file generates // ssa/rewritegeneric.go.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 16 22:21:05 UTC 2024 - 135.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/AMD64.rules
// Special-case bit patterns on first/last bit. // generic.rules changes ANDs of high-part/low-part masks into a couple of shifts, // for instance: // x & 0xFFFF0000 -> (x >> 16) << 16 // x & 0x80000000 -> (x >> 31) << 31 // // In case the mask is just one bit (like second example above), it conflicts // with the above rules to detect bit-testing / bit-clearing of first/last bit.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 12 19:38:41 UTC 2024 - 93.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
// // Note, y is always non-negative. // // Note, ISELZ is intentionally not used in lower. Where possible, ISEL is converted to ISELZ in late lower // after all the ISEL folding rules have been exercised. ((Rsh64U|Lsh64)x64 <t> x y) => (ISEL [0] (S(R|L)D <t> x y) (MOVDconst [0]) (CMPUconst y [64])) ((Rsh64U|Lsh64)x32 <t> x y) => (ISEL [0] (S(R|L)D <t> x y) (MOVDconst [0]) (CMPWUconst y [64]))
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
// shifts // hardware instruction uses only the low 6 bits of the shift // we compare to 64 to ensure Go semantics for large shifts // Rules about rotates with non-const shift are based on the following rules, // if the following rules change, please also modify the rules based on them. // check shiftIsBounded first, if shift value is proved to be valid then we // can do the shift directly. // left shift
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
testing/architecture-test/src/changes/archunit-store/stored.rules
Anže Sodja <******@****.***> 1717576978 +0200
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Wed Jun 05 08:43:33 UTC 2024 - 3.8K bytes - Viewed (0)