func IsLoong64AMO(op obj.As) bool {
	return loong64.IsAtomicInst(op)
}

var loong64ElemExtMap = map[string]int16{
	"B":  loong64.ARNG_B,
	"H":  loong64.ARNG_H,
	"W":  loong64.ARNG_W,
	"V":  loong64.ARNG_V,
	"BU": loong64.ARNG_BU,
	"HU": loong64.ARNG_HU,
	"WU": loong64.ARNG_WU,
	"VU": loong64.ARNG_VU,
}

var loong64LsxArngExtMap = map[string]int16{
	"B16": loong64.ARNG_16B,
	"H8":  loong64.ARNG_8H,
	"W4":  loong64.ARNG_4W,

	for i := loong64.REG_R0; i <= loong64.REG_R31; i++ {
		register[obj.Rconv(i)] = int16(i)
	}

	for i := loong64.REG_F0; i <= loong64.REG_F31; i++ {
		register[obj.Rconv(i)] = int16(i)
	}

	for i := loong64.REG_FCSR0; i <= loong64.REG_FCSR31; i++ {
		register[obj.Rconv(i)] = int16(i)
	}

	for i := loong64.REG_FCC0; i <= loong64.REG_FCC31; i++ {
		register[obj.Rconv(i)] = int16(i)

	testEndToEnd(t, "loong64", "loong64enc1")
	testEndToEnd(t, "loong64", "loong64enc2")
	testEndToEnd(t, "loong64", "loong64enc3")
	testEndToEnd(t, "loong64", "loong64enc4")
	testEndToEnd(t, "loong64", "loong64enc5")
	testEndToEnd(t, "loong64", "loong64enc6")
	testEndToEnd(t, "loong64", "loong64")
}

func TestLOONG64Errors(t *testing.T) {
	testErrors(t, "loong64", "loong64error")
}

			if arch.IsMIPSCMP(op) || arch.IsMIPSMUL(op) {
				prog.From = a[0]
				prog.Reg = p.getRegister(prog, op, &a[1])
				break
			}
		} else if p.arch.Family == sys.Loong64 {
			if arch.IsLoong64RDTIME(op) {
				// The Loong64 RDTIME family of instructions is a bit special,
				// in that both its register operands are outputs
				prog.To = a[0]
				if a[1].Type != obj.TYPE_REG {

		}
		for {
			tok = p.nextToken()
			if len(operands) == 0 && len(items) == 0 {
				if p.arch.InFamily(sys.ARM, sys.ARM64, sys.AMD64, sys.I386, sys.Loong64, sys.RISCV64) && tok == '.' {
					// Suffixes: ARM conditionals, Loong64 vector instructions, RISCV rounding mode or x86 modifiers.
					tok = p.nextToken()
					str := p.lex.Text()
					if tok != scanner.Ident {

	ADDV16	$(8<<16), R4, R5	// ADDV16	$524288, R4, R5		// 85200010
	ADDV16	$(32767<<16), R4, R5	// ADDV16	$2147418112, R4, R5	// 85fcff11
	ADDV16	$(16<<16), R4		// ADDV16	$1048576, R4		// 84400010

	// Loong64 atomic memory access instructions
	AMSWAPB		R14, (R13), R12 // ac395c38
	AMSWAPH		R14, (R13), R12 // acb95c38
	AMSWAPW		R14, (R13), R12 // ac396038
	AMSWAPV		R14, (R13), R12 // acb96038

to a specified boundary by padding with no-op instructions.
</p>

<p>
It is currently supported on arm64, amd64, ppc64, loong64 and riscv64.

For example, the start of the <code>MOVD</code> instruction below is aligned to 32 bytes:
<pre>
PCALIGN $32
MOVD $2, R0
</pre>
</p>

NOSPLIT|NOFRAME, $0 MOVD dst+0(FP), R0 MOVD a+8(FP), R1 MOVD b+16(FP), R2 MOVD n+24(FP), R3 CMP $64, R3 BLT tail loop_64: VLD1.P 64(R1), [V0.B16, V1.B16, V2.B16, V3.B16] VLD1.P 64(R2), [V4.B16, V5.B16, V6.B16, V7.B16] VEOR V0.B16, V4.B16, V4.B16 VEOR V1.B16, V5.B16, V5.B16 VEOR V2.B16, V6.B16, V6.B16 VEOR V3.B16, V7.B16, V7.B16 VST1.P [V4.B16, V5.B16, V6.B16, V7.B16], 64(R0) SUBS $64, R3 CMP $64, R3 BGE loop_64 tail: // quick end CBZ R3, end TBZ $5, R3, less_than32 VLD1.P 32(R1), [V0.B16, V1.B16] VLD1.P 32(R2),...

NOSPLIT|NOFRAME, $0 MOVD dst+0(FP), R0 MOVD a+8(FP), R1 MOVD b+16(FP), R2 MOVD n+24(FP), R3 CMP $64, R3 BLT tail loop_64: VLD1.P 64(R1), [V0.B16, V1.B16, V2.B16, V3.B16] VLD1.P 64(R2), [V4.B16, V5.B16, V6.B16, V7.B16] VEOR V0.B16, V4.B16, V4.B16 VEOR V1.B16, V5.B16, V5.B16 VEOR V2.B16, V6.B16, V6.B16 VEOR V3.B16, V7.B16, V7.B16 VST1.P [V4.B16, V5.B16, V6.B16, V7.B16], 64(R0) SUBS $64, R3 CMP $64, R3 BGE loop_64 tail: // quick end CBZ R3, end TBZ $5, R3, less_than32 VLD1.P 32(R1), [V0.B16, V1.B16] VLD1.P 32(R2),...