VSPLTW $1, Y0, YDIG // VREPF // VMALHF X0, YDIG, T0, ADD1H // VMALHF X1, YDIG, T1, ADD2H // VMALF X0, YDIG, T0, ADD1 // T0 Free->ADD1 // VMALF X1, YDIG, T1, ADD2 // T1 Free->ADD2 VMULT_ADD(X0, YDIG, T0, ONE, ADD1, ADD1H) VMULT_ADD(X1, YDIG, T1, ONE, ADD2, ADD2H) VSPLTW $0, Y0, YDIG // VREPF // VMALF X0, YDIG, ADD1H, ADD3 // VMALF X1, YDIG, ADD2H, ADD4 // VMALHF X0, YDIG, ADD1H, ADD3H // ADD1H Free->ADD3H // VMALHF X1, YDIG, ADD2H, ADD4H // ADD2H Free->ADD4H , YDIG Free->ZER VMULT_ADD(X0, YDIG, ADD1H,...

  VerifyFDef({"add1_0", "add2_0"}, M({{"feed1"}, {"feed2"}, {"feed3"}}),
             M({{"add1"}, {"add2"}}),
             {{"feed1", "add1_0:0"},
              {"feed2", "add1_0:1"},
              {"add1_0:sum:0", "add2_0:0"},
              {"feed3", "add2_0:1"},
              {"add1_0:sum:0", "add1"},
              {"add2_0:sum:0", "add2"}},
             {});
}

*   Enable JIT-compiled i64-indexed kernels on GPU for large tensors with more than 2**32 elements.
    *   Unary GPU kernels: Abs, Atanh, Acos, Acosh, Asin, Asinh, Atan, Cos, Cosh, Sin, Sinh, Tan, Tanh.
    *   Binary GPU kernels: AddV2, Sub, Div, DivNoNan, Mul, MulNoNan, FloorDiv, Equal, NotEqual, Greater, GreaterEqual, LessEqual, Less.

* `tf.lite`
    * Add experimental supports conversion of models that may be larger than 2GB before buffer deduplication