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android/guava/src/com/google/common/xml/XmlEscapers.java
* respectively. Any other non-ASCII characters appearing in the input will be preserved in the * output. * * <p>This escaper does not treat surrogate pairs specially and does not perform Unicode * validation on its input. */ @SuppressWarnings("EscapedEntity") // We do mean for the user to see 	" etc.Registered: Fri Dec 26 12:43:10 UTC 2025 - Last Modified: Thu Sep 11 17:06:34 UTC 2025 - 6.4K bytes - Viewed (0) -
guava-tests/test/com/google/common/xml/XmlEscapersTest.java
// Test all escapes assertEquals( "a"b<c>d&e"f'", xmlAttributeEscaper.escape("a\"b<c>d&e\"f'")); // Test '\t', '\n' and '\r' are escaped. assertEquals("a	b
c
d", xmlAttributeEscaper.escape("a\tb\nc\rd")); } // Helper to assert common properties of xml escapers. static void assertBasicXmlEscaper(Registered: Fri Dec 26 12:43:10 UTC 2025 - Last Modified: Fri Dec 05 22:03:28 UTC 2025 - 4.8K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
CANDI $31, X10 // 7d89 // 26.5.3: Compressed Integer Register-Register Operations CMV X6, X5 // 9a82 CADD X9, X8 // 2694 CAND X9, X8 // 658c COR X9, X8 // 458c CXOR X9, X8 // 258c CSUB X9, X8 // 058c CADDW X9, X8 // 259c CSUBW X9, X8 // 059c // 26.5.5: Compressed NOP Instruction CNOP // 0100 // 26.5.6: Compressed Breakpoint Instruction
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 73.7K bytes - Viewed (0) -
lib/fips140/v1.1.0-rc1.zip
MOVOU bswapMask<>+0(SB), X0 MOVQ SI, X1 PINSRQ $0x01, DI, X1 MOVAPS X1, X8 PSHUFB X0, X1 MOVQ SI, R8 ADDQ $0x07, R8 JC ctr8_slow XORQ R8, R8 INCQ R8 PXOR X9, X9 PINSRQ $0x00, R8, X9 PADDQ X9, X8 MOVAPS X8, X2 PADDQ X9, X8 MOVAPS X8, X3 PADDQ X9, X8 MOVAPS X8, X4 PADDQ X9, X8 MOVAPS X8, X5 PADDQ X9, X8 MOVAPS X8, X6 PADDQ X9, X8 MOVAPS X8, X7 PADDQ X9, X8 MOVAPS X8, X8 JMP ctr8_done ctr8_slow: ADDQ $0x01, SI ADCQ $0x00, DI MOVQ SI, X2 PINSRQ $0x01, DI, X2 ADDQ $0x01, SI ADCQ $0x00, DI MOVQ SI, X3 PINSRQ...
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Dec 11 16:27:41 UTC 2025 - 663K bytes - Viewed (0) -
lib/fips140/v1.0.0-c2097c7c.zip
:= arg1[5] x6 := arg1[6] x7 := arg1[7] x8 := arg1[8] x9 := arg1[0] var x10 uint64 var x11 uint64 x11, x10 = bits.Mul64(x9, arg2[8]) var x12 uint64 var x13 uint64 x13, x12 = bits.Mul64(x9, arg2[7]) var x14 uint64 var x15 uint64 x15, x14 = bits.Mul64(x9, arg2[6]) var x16 uint64 var x17 uint64 x17, x16 = bits.Mul64(x9, arg2[5]) var x18 uint64 var x19 uint64 x19, x18 = bits.Mul64(x9, arg2[4]) var x20 uint64 var x21 uint64 x21, x20 = bits.Mul64(x9, arg2[3]) var x22 uint64 var x23 uint64 x23, x22 = bits.Mul64(x9,...
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Sep 25 19:53:19 UTC 2025 - 642.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
VMOVQ R4, V3.B[1] // 8384eb72 VMOVQ R5, V4.B[3] // a48ceb72 VMOVQ R6, V5.H[2] // c5c8eb72 VMOVQ R7, V6.W[2] // e6e8eb72 VMOVQ R8, V7.V[1] // 07f5eb72 XVMOVQ R7, X9.W[2] // e9c8eb76 XVMOVQ R8, X10.V[2] // 0ae9eb76 // Duplicate general-purpose register to vector VMOVQ R4, V2.B16 // 82009f72 VMOVQ R5, V3.H8 // a3049f72 VMOVQ R6, V4.W4 // c4089f72
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 27 00:46:52 UTC 2025 - 44.5K bytes - Viewed (0)