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Results 1 - 5 of 5 for X5 (0.31 sec)

  1. src/cmd/asm/internal/asm/testdata/riscv64.s

    	ADD	$-2048, X5, X6				// 13830280
    	ADD	$2047, X5				// 9382f27f
    	ADD	$-2048, X5				// 93820280
    
    	SLT	X6, X5, X7				// b3a36200
    	SLT	$55, X5, X7				// 93a37203
    	SLTU	X6, X5, X7				// b3b36200
    	SLTU	$55, X5, X7				// 93b37203
    
    	AND	X6, X5, X7				// b3f36200
    	AND	X5, X6					// 33735300
    	AND	$1, X5, X6				// 13f31200
    	AND	$1, X5					// 93f21200
    	OR	X6, X5, X7				// b3e36200
    	OR	X5, X6					// 33635300
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed May 21 14:19:19 UTC 2025
    - 49.1K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/riscv64error.s

    	RORI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SLLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SRLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SRAI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    	RORIW	$32, X5, X6			// ERROR "immediate out of range 0 to 31"
    	SLLIW	$32, X5, X6			// ERROR "immediate out of range 0 to 31"
    	SRLIW	$32, X5, X6			// ERROR "immediate out of range 0 to 31"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Thu May 08 08:53:43 UTC 2025
    - 24.8K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/riscv64validation.s

    // the validate function from being run and TestRISCVValidation will report missing
    // errors.
    
    TEXT validation(SB),$0
    	SRLI	$1, X5, F1			// ERROR "expected integer register in rd position but got non-integer register F1"
    	SRLI	$1, F1, X5			// ERROR "expected integer register in rs1 position but got non-integer register F1"
    
    	//
    	// "V" Standard Extension for Vector Operations, Version 1.0
    	//
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed May 21 14:19:19 UTC 2025
    - 31.6K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/asm.go

    			x2 := int64(p.getRegister(prog, op, &a[2]))
    			x3 := int64(p.getRegister(prog, op, &a[3]))
    			x4 := int64(p.getRegister(prog, op, &a[4]))
    			x5 := p.getConstant(prog, op, &a[5])
    			// Cond is handled specially for this instruction.
    			offset, MRC, ok := arch.ARMMRCOffset(op, cond, x0, x1, x2, x3, x4, x5)
    			if !ok {
    				p.errorf("unrecognized condition code .%q", cond)
    			}
    			prog.To.Offset = offset
    			cond = ""
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 05 17:31:25 UTC 2025
    - 26.2K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/loong64enc1.s

    	XVMOVQ		X3, 3(R4)       // 830cc02c
    	XVMOVQ		X4, 2040(R4)    // 84e0df2c
    	XVMOVQ		X5, -2040(R4)   // 8520e02c
    	XVMOVQ		X6, y+16(FP)    // 0660c02c
    	XVMOVQ		X7, x+2030(FP)  // 07d8df2c
    	XVMOVQ		(R4), X2        // 8200802c
    	XVMOVQ		3(R4), X3       // 830c802c
    	XVMOVQ		2044(R4), X4    // 84f09f2c
    	XVMOVQ		-2044(R4), X5   // 8510a02c
    	XVMOVQ		y+16(FP), X6    // 0660802c
    	XVMOVQ		x+2030(FP), X7  // 07d89f2c
    
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Thu Sep 04 19:24:25 UTC 2025
    - 35.5K bytes
    - Viewed (0)
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