VSETVLI	X10, E32, MF8, TA, MA, X12		// 5776550d
	VSETVLI	X10, E32, MF4, TA, MA, X12		// 5776650d
	VSETVLI	X10, E32, MF2, TA, MA, X12		// 5776750d
	VSETVLI	X10, E32, M1, TA, MA, X12		// 5776050d
	VSETVLI	$15, E32, M1, TA, MA, X12		// 57f607cd
	VSETIVLI $0, E32, M1, TA, MA, X12		// 577600cd
	VSETIVLI $15, E32, M1, TA, MA, X12		// 57f607cd
	VSETIVLI $31, E32, M1, TA, MA, X12		// 57f60fcd
	VSETVL	X10, X11, X12				// 57f6a580

	//
	// "V" Standard Extension for Vector Operations, Version 1.0
	//
	VSETVLI		$32, E16, M1, TU, MU, X12	// ERROR "must be in range [0, 31] (5 bits)"
	VSETVLI		$-1, E32, M2, TA, MA, X12	// ERROR "must be in range [0, 31] (5 bits)"
	VSETVL		X10, X11			// ERROR "expected integer register in rs1 position"
	VLE8V		(X10), X10			// ERROR "expected vector register in vd position"

	MOVWU	X5, (X6)			// ERROR "unsupported unsigned store"
	MOVF	F0, F1, F2			// ERROR "illegal MOV instruction"
	MOVD	F0, F1, F2			// ERROR "illegal MOV instruction"
	MOV	X10, X11, X12			// ERROR "illegal MOV instruction"
	MOVW	X10, X11, X12			// ERROR "illegal MOV instruction"
	RORI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
	SLLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"