CJR	X0					// ERROR "cannot use register X0 in rs1"
	CJR	X10, X11				// ERROR "expected no register in rs2"
	CJALR	X0					// ERROR "cannot use register X0 in rs1"
	CJALR	X10, X11				// ERROR "expected no register in rd"
	CBEQZ	X5, 1(PC)				// ERROR "expected integer prime register in rs1"
	CBNEZ	X5, 1(PC)				// ERROR "expected integer prime register in rs1"
	CLI	$3, X0					// ERROR "cannot use register X0 in rd"

AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 ADDQ $0x20, CX enc128: MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 32(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 48(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 64(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 80(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3...

	RET
TEXT ·a28(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	PEXTRD $0, X0, R15
	ADDQ $1, R15
	RET
TEXT ·a29(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0
	VPEXTRD $0, X0, R15
	ADDQ $1, R15
	RET
TEXT ·a30(SB), 0, $0-0
	CMPL runtime·writeBarrier(SB), $0

// license that can be found in the LICENSE file.

TEXT errors(SB),$0
	CSRRC	(X10), CYCLE, X5		// ERROR "integer register or immediate expected for 1st operand"
	CSRRC	X0, TU, X5			// ERROR "unknown CSR"
	CSRRC	X0, CYCLE			// ERROR "missing CSR name"
	CSRRC	X0, CYCLE, (X10)		// ERROR "needs an integer register output"
	CSRRC	$-1, TIME, X15			// ERROR "immediate out of range 0 to 31"
	CSRRCI	$32, TIME, X15			// ERROR "immediate out of range 0 to 31"

      h ^= fingerprint(buf, bufLen);
      h = remix(h);
      buf[bufLen++] = getChar(h);

      int x0 = buf[bufLen - 1] & 0xff;
      int x1 = buf[bufLen - 2] & 0xff;
      int x2 = buf[bufLen - 3] & 0xff;
      int x3 = buf[bufLen / 2] & 0xff;
      buf[((x0 << 16) + (x1 << 8) + x2) % bufLen] ^= x3;
      buf[((x1 << 16) + (x2 << 8) + x3) % bufLen] ^= i % 256;
    }

	// 7.1: CSR Instructions
	CSRRC	X0, CYCLE, X5				// f33200c0
	CSRRC	X0, CYCLE, X0				// 733000c0
	CSRRC	X10, CYCLE, X5				// f33205c0
	CSRRC	$2, TIME, X5				// f37211c0
	CSRRCI	$2, TIME, X5				// f37211c0
	CSRRS	X0, CYCLE, X5				// f32200c0
	CSRRS	X0, CYCLE, X0				// 732000c0
	CSRRS	X10, CYCLE, X5				// f32205c0
	CSRRS	$2, TIME, X5				// f36211c0
	CSRRS	X0, VLENB, X5				// f32220c2

	VMOVQ		-12(R4), V2.W4	// 82f42f30
	VMOVQ		(R4), V3.V2	// 83001030
	VMOVQ		24(R4), V3.V2	// 830c1030
	VMOVQ		-16(R4), V3.V2	// 83f81730
	XVMOVQ		(R4), X0.B32	// 80008032
	XVMOVQ		1(R4), X0.B32	// 80048032
	XVMOVQ		-5(R4), X0.B32	// 80ecbf32
	XVMOVQ		(R4), X1.H16	// 81004032
	XVMOVQ		2(R4), X1.H16	// 81044032
	XVMOVQ		-10(R4), X1.H16	// 81ec5f32
	XVMOVQ		(R4), X2.W8	// 82002032

    @Test
    public void test_mergeResponseData_keyConflict() {
        Map<String, Object> dataMap = new HashMap<>();
        dataMap.put("x", "X0");
        Map<String, Object> responseDataMap = new HashMap<>();
        responseDataMap.put("x", "X1");

        indexUpdateCallback.mergeResponseData(dataMap, responseDataMap);

        assertEquals(1, dataMap.size());

			prog.To.Type = obj.TYPE_CONST
			x0 := p.getConstant(prog, op, &a[0])
			x1 := p.getConstant(prog, op, &a[1])
			x2 := int64(p.getRegister(prog, op, &a[2]))
			x3 := int64(p.getRegister(prog, op, &a[3]))
			x4 := int64(p.getRegister(prog, op, &a[4]))
			x5 := p.getConstant(prog, op, &a[5])
			// Cond is handled specially for this instruction.
			offset, MRC, ok := arch.ARMMRCOffset(op, cond, x0, x1, x2, x3, x4, x5)
			if !ok {