- Sort Score
- Result 10 results
- Languages All
Results 1 - 9 of 9 for VSR (0.05 sec)
-
src/cmd/internal/obj/ppc64/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 6.7K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/a.out.go
REG_CR4EQ REG_CR4SO REG_CR5LT REG_CR5GT REG_CR5EQ REG_CR5SO REG_CR6LT REG_CR6GT REG_CR6EQ REG_CR6SO REG_CR7LT REG_CR7GT REG_CR7EQ REG_CR7SO /* Align FPR and VSR vectors such that when masked with 0x3F they produce an equivalent VSX register. */ /* F0=4160 ... F31=4191 */ REG_F0 REG_F1 REG_F2 REG_F3 REG_F4 REG_F5 REG_F6 REG_F7 REG_F8
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
{as: ASTXSIWX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4}, /* vsx scalar as integer store, xx1-form */ /* VSX move from VSR */ {as: AMFVSRD, a1: C_VSREG, a6: C_REG, type_: 88, size: 4}, {as: AMFVSRD, a1: C_FREG, a6: C_REG, type_: 88, size: 4}, /* VSX move to VSR */ {as: AMTVSRD, a1: C_REG, a6: C_VSREG, type_: 104, size: 4}, {as: AMTVSRD, a1: C_REG, a6: C_FREG, type_: 104, size: 4},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0) -
src/crypto/aes/asm_ppc64x.s
VXOR IN0, KEY, IN0 // vxor 1,1,3 STXVD2X IN0, (R0+OUTENC) STXVD2X IN0, (R0+OUTDEC) RET l192: LXSDX (INP+R0), IN1 // Load next 8 bytes into upper half of VSR. XXBRD_ON_LE(IN1, IN1) // and convert to BE ordering on LE hosts. MOVD $4, CNT // li 7,4 STXVD2X IN0, (R0+OUTENC) STXVD2X IN0, (R0+OUTDEC) ADD $16, OUTENC, OUTENC
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 20 18:05:32 UTC 2024 - 18.6K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_ppc64le.s
VSEL T1, X1, SEL1, T1 \ VSEL T2, ZER, SEL1, T2 \ \ VSLDOI $15, T2, ZER, TT1 \ VSLDOI $15, T1, ZER, TT0 \ VSPLTISB $1, SEL1 \ VSR T0, SEL1, T0 \ // VSRL VSR T1, SEL1, T1 \ VSPLTISB $7, SEL1 \ // VREPIB VSL TT0, SEL1, TT0 \ VSL TT1, SEL1, TT1 \ VOR T0, TT0, T0 \ VOR T1, TT1, T1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 56.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/ppc64.s
VSRB V1, V2, V3 // 10611204 VSRH V1, V2, V3 // 10611244 VSRW V1, V2, V3 // 10611284 VSRD V1, V2, V3 // 106116c4 VSR V1, V2, V3 // 106112c4 VSRO V1, V2, V3 // 1061144c VSLD V1, V2, V3 // 106115c4 VSRAB V1, V2, V3 // 10611304 VSRAH V1, V2, V3 // 10611344
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 21:53:50 UTC 2024 - 50.2K bytes - Viewed (0) -
guava/src/com/google/thirdparty/publicsuffix/PublicSuffixPatterns.java
a,niln&igol,okoob,?tupmocegde,virdhsalfno,?ilressem,k&orgn,relc,?le&crev,napysae,?maerdepyt,naecolatigidno,poon,r&cne,emarf,?sserpirots,t&i&belet,l&maerts,per:.di,,??xenw,?wolfrettulf,yfilten,??ra&a?hs??u&ekam?llag?org!.esruocsid,cts?kouk?nayalo???vsr?xece4ibgm--nx??q&a!3a9y--nx??g?i!.&gro?lim?moc?ten?ude?vog???m?se??r&a!.&a&cisum?sanes??bog?gro?l&autum?im??moc!.topsgolb,?pooc?rut?t&e&b?n??ni??ude?vog??4d5a4prebgm--nx?b?c?eydoog?los?t&at?s!uen???ugaj??b!.&21g?a&b&a&coros?iuc??itiruc??cnogoas?dic...
Registered: Wed Jun 12 16:38:11 UTC 2024 - Last Modified: Thu Mar 21 21:04:43 UTC 2024 - 72.4K bytes - Viewed (0) -
android/guava/src/com/google/thirdparty/publicsuffix/PublicSuffixPatterns.java
a,niln&igol,okoob,?tupmocegde,virdhsalfno,?ilressem,k&orgn,relc,?le&crev,napysae,?maerdepyt,naecolatigidno,poon,r&cne,emarf,?sserpirots,t&i&belet,l&maerts,per:.di,,??xenw,?wolfrettulf,yfilten,??ra&a?hs??u&ekam?llag?org!.esruocsid,cts?kouk?nayalo???vsr?xece4ibgm--nx??q&a!3a9y--nx??g?i!.&gro?lim?moc?ten?ude?vog???m?se??r&a!.&a&cisum?sanes??bog?gro?l&autum?im??moc!.topsgolb,?pooc?rut?t&e&b?n??ni??ude?vog??4d5a4prebgm--nx?b?c?eydoog?los?t&at?s!uen???ugaj??b!.&21g?a&b&a&coros?iuc??itiruc??cnogoas?dic...
Registered: Wed Jun 12 16:38:11 UTC 2024 - Last Modified: Thu Mar 21 21:04:43 UTC 2024 - 72.4K bytes - Viewed (1) -
src/cmd/internal/obj/x86/asm6.go
ctxt.Diag("unsupported SAE: %v", p) } evexB = 1 } if rm != nil && regrex[rm.Index]&RxrEvex != 0 { evexV = 0 } else if v != nil && regrex[v.Reg]&RxrEvex != 0 { evexV = 0 // VSR selector 5th bit. } if k != nil { evexA = byte(reg[k.Reg]) } // P2 = [z][L'L][b][V'][aaa] p2 := (evexZ << 7) | (evexLL << 5) | (evexB << 4) | (evexV << 3) | (evexA << 0)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 15:44:14 UTC 2024 - 146.9K bytes - Viewed (0)