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Results 1 - 4 of 4 for V12 (0.28 sec)

  2. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/arm64error.s 

    	VMOV	V8.D[0], V12.S[1]                                // ERROR "operand mismatch"
	VMOV	V8.D[0], V12.H[1]                                // ERROR "operand mismatch"
	VMOV	V8.D[0], V12.B[1]                                // ERROR "operand mismatch"
	VMOV	V8.S[0], V12.H[1]                                // ERROR "operand mismatch"
	VMOV	V8.S[0], V12.B[1]                                // ERROR "operand mismatch"
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 37.9K bytes
    - Viewed (0)
  3. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/arm64.s 

    	VADD	V1, V3, V3                      // 6384e15e
	VSUB	V12, V30, V30                   // de87ec7e
	VSUB	V12, V20, V30                   // 9e86ec7e
	VFMLA	V1.D2, V12.D2, V1.D2            // 81cd614e
	VFMLA	V1.S2, V12.S2, V1.S2            // 81cd210e
	VFMLA	V1.S4, V12.S4, V1.S4            // 81cd214e
	VFMLS	V1.D2, V12.D2, V1.D2            // 81cde14e
	VFMLS	V1.S2, V12.S2, V1.S2            // 81cda10e
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 95.3K bytes
    - Viewed (0)
  4. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/s390x.s 

    	VGEF	$0, 2048(R15)(V1*1), V2 // e721f8000013
	VSCEF	$0, V2, 4095(R15)(V1*1) // e721ffff001b
	VLL	R0, (R15), V1           // e710f0000037
	VSTL	R0, V16, (R15)          // e700f000083f
	VGMH	$8, $16, V12            // e7c008101046
	VLEIB	$15, $255, V0           // e70000fff040
	VLEIH	$7, $-32768, V15        // e7f080007041
	VLEIF	$2, $-43, V16           // e700ffd52843
	VLEIG	$1, $32767, V31         // e7f07fff1842
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Jul 30 19:29:15 UTC 2025
    - 22.9K bytes
    - Viewed (0)
  5. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/riscv64.s 

    	VRGATHERVI	$16, V2, V0, V3			// d7312830

	// 31.16.5: Vector Compress Instruction
	VCOMPRESSVM	V1, V2, V3			// d7a1205e

	// 31.16.6: Whole Vector Register Move
	VMV1RV		V2, V1				// d730209e
	VMV2RV		V12, V10			// 57b5c09e
	VMV4RV		V8, V4				// 57b2819e
	VMV8RV		V8, V0				// 57b0839e

	//
	// Privileged ISA
	//

	// 3.3.1: Environment Call and Breakpoint
	ECALL						// 73000000
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed May 21 14:19:19 UTC 2025
    - 49.1K bytes
    - Viewed (0)
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