SUBSW R2.SXTH<<3, R13, R6                  // a6ad226b
	SUBS R21.UXTX<<2, R27, R4                  // 646b35eb
	SUBSW $(44<<12), R6, R9                    // SUBSW $180224, R6, R9         // c9b04071
	SUBS $(1804<<12), R13, R9                  // SUBS $7389184, R13, R9        // a9315cf1
	SUBSW R22->28, R6, R7                      // c770966b
	SUBSW R22>>28, R6, R7                      // c770566b

high x[i+1]*y ADDC R17, R14 ADDZE R15 ADDC R9, R14 ADDZE R15, R9 MULLD R5, R18, R16 // low x[i+2]*y MULHDU R5, R18, R17 // high x[i+2]*y ADDC R19, R16 ADDZE R17 ADDC R9, R16 ADDZE R17, R9 MULLD R5, R20, R18 // low x[i+3]*y MULHDU R5, R20, R19 // high x[i+3]*y ADDC R21, R18 ADDZE R19 ADDC R9, R18 ADDZE R19, R9 MOVD R10, 0(R3) // z[i] MOVD R14, 8(R3) // z[i+1] MOVD R16, 16(R3) // z[i+2] MOVD R18, 24(R3) // z[i+3] ADD $32, R3 ADD $32, R4 BDNZ loop done: MOVD R9, c+24(FP) RET golang.org/fips140@v1.26.0...

	CASALW	R5, (RSP), R7                        // e7ffe588
	CASALH	ZR, (R5), R8                         // a8fcff48
	CASALB	R8, (R9), ZR                         // 3ffde808
	CASPD	(R30, ZR), (RSP), (R8, R9)           // e87f3e48
	CASPW	(R6, R7), (R8), (R4, R5)             // 047d2608
	CASPD	(R2, R3), (R2), (R8, R9)             // 487c2248

// RET
	RET                                        // c0035fd6
	RET R0					   // 00005fd6

	VLD1.P	(R8)(R9.SXTX<<2), [V2.B16]                       // ERROR "invalid extended register"
	VLD1.P	(R8)(R9<<2), [V2.B16]                            // ERROR "invalid extended register"
	VST1.P	[V1.B16], (R8)(R9.UXTW)                          // ERROR "invalid extended register"
	VST1.P	[V1.B16], (R8)(R9<<1)                            // ERROR "invalid extended register"

The range of registers is specified by a start register and an end register.
For example, <code>LMG</code> <code>(R9),</code> <code>R5,</code> <code>R7</code> would load
<code>R5</code>, <code>R6</code> and <code>R7</code> with the 64-bit values at
<code>0(R9)</code>, <code>8(R9)</code> and <code>16(R9)</code> respectively.
</p>

<p>
Storage-and-storage instructions such as <code>MVC</code> and <code>XC</code> are written

		Type:  obj.TYPE_BRANCH,
		Index: 0,
	}
	addr.Val = target
}

func isARM64SVE(op obj.As) bool {
	return op > arm64.ASVESTART
}

// asmInstruction assembles an instruction.
// MOVW R9, (R10)
func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
	// fmt.Printf("%s %+v\n", op, a)
	prog := &obj.Prog{
		Ctxt: p.ctxt,
		Pos:  p.pos(),
		As:   op,
	}
	switch len(a) {