//TODO STTRB -28(R23), R16                 // f04a1e38
	//TODO STTRH 9(R10), R19                   // 53990078
	STXP (R1, R2), (R3), R10                   // 61082ac8
	STXP (R1, R2), (RSP), R10                  // e10b2ac8
	STXPW (R1, R2), (R3), R10                  // 61082a88
	STXPW (R1, R2), (RSP), R10                 // e10b2a88
	STXRW R2, (R19), R20                       // 627e1488

MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 172(SP) MOVOU X11, 176(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 188(SP) MOVOU X11, 192(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 204(SP) MOVOU X11, 208(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 220(SP) MOVOU X11, 224(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL R11, 236(SP) MOVOU X11, 240(SP) ADDL $0x01, R10 MOVL R10, R11 XORL R12, R11 BSWAPL R11 MOVL...

	STLXP	(R6, R3), (R10), R2                  // 468d22c8
	STLXPW	(R6, R11), (R22), R21                // c6ae3588
	STLXRW	R1, (R0), R3                         // 01fc0388
	STXP	(R1, R2), (R3), R10                  // 61082ac8
	STXP	(R1, R2), (RSP), R10                 // e10b2ac8
	STXPW	(R1, R2), (R3), R10                  // 61082a88
	STXPW	(R1, R2), (RSP), R10                 // e10b2a88

	MOVD	(R3)(R7.SXTX<<2), R8                             // ERROR "invalid index shift amount"
	MOVWU	(R5)(R4.UXTW<<3), R10                            // ERROR "invalid index shift amount"
	MOVWU	(R5)(R4<<1), R10                                 // ERROR "invalid index shift amount"
	MOVB	(R5)(R4.SXTW<<5), R10                            // ERROR "invalid index shift amount"

</p>

<h3 id="arm">ARM</h3>

<p>
The registers <code>R10</code> and <code>R11</code>
are reserved by the compiler and linker.
</p>

<p>
<code>R10</code> points to the <code>g</code> (goroutine) structure.
Within assembler source code, this pointer must be referred to as <code>g</code>;
the name <code>R10</code> is not recognized.
</p>

<p>

	// Note that there is no list of names as there is for x86.
	for i := arm.REG_R0; i < arm.REG_SPSR; i++ {
		register[obj.Rconv(i)] = int16(i)
	}
	// Avoid unintentionally clobbering g using R10.
	delete(register, "R10")
	register["g"] = arm.REG_R10
	for i := 0; i < 16; i++ {
		register[fmt.Sprintf("C%d", i)] = int16(i)
	}

	// Pseudo-registers.
	register["SB"] = RSB
	register["FP"] = RFP

	p.expectOperandEnd()
	return
}

// atStartOfRegister reports whether the parser is at the start of a register definition.
func (p *Parser) atStartOfRegister(name string) bool {
	// Simple register: R10.
	_, present := p.arch.Register[name]
	if present {
		return true
	}
	// Parenthesized register: R(10).
	return p.arch.RegisterPrefix[name] && p.peek() == '('
}

		Type:  obj.TYPE_BRANCH,
		Index: 0,
	}
	addr.Val = target
}

func isARM64SVE(op obj.As) bool {
	return op > arm64.ASVESTART
}

// asmInstruction assembles an instruction.
// MOVW R9, (R10)
func (p *Parser) asmInstruction(op obj.As, cond string, a []obj.Addr) {
	// fmt.Printf("%s %+v\n", op, a)
	prog := &obj.Prog{
		Ctxt: p.ctxt,
		Pos:  p.pos(),
		As:   op,
	}
	switch len(a) {
	case 0: