class PropertiesAsMapTest {

    @Test
    void testPropertiesAsMap() {
        Properties props = new Properties();
        props.setProperty("foo1", "bar1");
        props.setProperty("foo2", "bar2");
        PropertiesAsMap pam = new PropertiesAsMap(props);
        assertEquals(2, pam.size());
        Set<Entry<String, String>> set = pam.entrySet();
        assertNotNull(set);
        assertEquals(2, set.size());

   *
   * <p>For example:
   *
   * {@snippet :
   * Streams.zip(
   *   Stream.of("foo1", "foo2", "foo3"),
   *   Stream.of("bar1", "bar2"),
   *   (arg1, arg2) -> arg1 + ":" + arg2)
   * }
   *
   * <p>will return {@code Stream.of("foo1:bar1", "foo2:bar2")}.
   *
   * <p>The resulting stream will only be as long as the shorter of the two input streams; if one

   *
   * <p>For example:
   *
   * {@snippet :
   * Streams.zip(
   *   Stream.of("foo1", "foo2", "foo3"),
   *   Stream.of("bar1", "bar2"),
   *   (arg1, arg2) -> arg1 + ":" + arg2)
   * }
   *
   * <p>will return {@code Stream.of("foo1:bar1", "foo2:bar2")}.
   *
   * <p>The resulting stream will only be as long as the shorter of the two input streams; if one

T0, RED1, T0 // VAQ T0, RED1, T0 VADDECUQ T1, RED2, CAR1, CAR2 // VACCCQ T1, RED2, CAR1, CAR2 VADDEUQM T1, RED2, CAR1, T1 // VACQ T1, RED2, CAR1, T1 VADDUQM T2, CAR2, T2 // VAQ T2, CAR2, T2 // ---------- VSUBCUQ T0, PL, CAR1 // VSCBIQ PL, T0, CAR1 VSUBUQM T0, PL, TT0 // VSQ PL, T0, TT0 VSUBECUQ T1, PH, CAR1, CAR2 // VSBCBIQ T1, PH, CAR1, CAR2 VSUBEUQM T1, PH, CAR1, TT1 // VSBIQ T1, PH, CAR1, TT1 VSUBEUQM T2, ZER, CAR2, T2 // VSBIQ T2, ZER, CAR2, T2 VSEL TT0, T0, T2, T0 VSEL TT1, T1, T2, T1 // Reorder...

T0, RED1, T0 // VAQ T0, RED1, T0 VADDECUQ T1, RED2, CAR1, CAR2 // VACCCQ T1, RED2, CAR1, CAR2 VADDEUQM T1, RED2, CAR1, T1 // VACQ T1, RED2, CAR1, T1 VADDUQM T2, CAR2, T2 // VAQ T2, CAR2, T2 // ---------- VSUBCUQ T0, PL, CAR1 // VSCBIQ PL, T0, CAR1 VSUBUQM T0, PL, TT0 // VSQ PL, T0, TT0 VSUBECUQ T1, PH, CAR1, CAR2 // VSBCBIQ T1, PH, CAR1, CAR2 VSUBEUQM T1, PH, CAR1, TT1 // VSBIQ T1, PH, CAR1, TT1 VSUBEUQM T2, ZER, CAR2, T2 // VSBIQ T2, ZER, CAR2, T2 VSEL TT0, T0, T2, T0 VSEL TT1, T1, T2, T1 // Reorder...