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Results 1 - 6 of 6 for 16B (0.05 sec)
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src/text/tabwriter/tabwriter_test.go
"a\tb\tc\td\n" + "a\tb\tc\td\te\n", }, { "16b", 100, 100, 0, '\t', DiscardEmptyColumns, "a\vb\v\vd\n" + "a\vb\v\vd\ve\n" + "a\n" + "a\vb\vc\vd\n" + "a\vb\vc\vd\ve\n", "a\tb\td\n" + "a\tb\td\te\n" + "a\n" + "a\tb\tc\td\n" + "a\tb\tc\td\te\n", }, { "16b debug", 100, 100, 0, '\t', DiscardEmptyColumns | Debug, "a\vb\v\vd\n" +
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Feb 29 16:46:34 UTC 2024 - 13.8K bytes - Viewed (0) -
src/cmd/link/internal/ppc64/asm.go
if target.IsAIX() && rt == objabi.R_POWER_TLS_LE { // Fixup val, an addis/addi pair of instructions, which generate a 32b displacement // from the threadpointer (R13), into a 16b relocation. XCOFF only supports 16b // TLS LE relocations. Likewise, verify this is an addis/addi sequence. const expectedOpcodes = 0x3C00000038000000 const expectedOpmasks = 0xFC000000FC000000
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Mar 19 20:54:08 UTC 2024 - 63.7K bytes - Viewed (0) -
src/runtime/race_ppc64le.s
MOVD 0(R10), R11 MOVD g_m(R11), R3 MOVD m_p(R3), R3 MOVD p_raceprocctx(R3), R3 MOVD R3, (R4) RET rest: // Save registers according to the host PPC64 ABI // and reserve 16B for argument storage. STACK_AND_SAVE_HOST_TO_GO_ABI(16) // Load g, and switch to g0 if not already on it. MOVD runtimeĀ·tls_g(SB), R10 MOVD 0(R10), g MOVD g_m(g), R7 MOVD m_g0(R7), R8 CMP g, R8
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 18:37:29 UTC 2024 - 17K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm_test.go
{[]byte(x16pgm), "align=0x20", false}, // Increased alignment needed {[]byte(x32pgm), "align=0x40", false}, // Worst case alignment needed {[]byte(x64pgm), "align=0x0", true}, // 0 aligned is default (16B) alignment {[]byte(x64pgmA64), "align=0x40", true}, // extra alignment + nop {[]byte(x64pgmA32), "align=0x20", true}, // extra alignment + nop } for _, pgm := range pgms { tmpfile := filepath.Join(dir, "x.s")
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 09 22:14:57 UTC 2024 - 17.3K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/obj9.go
// The assembler can generate this opcode in 1 (on Power10) or 2 opcodes. // Otherwise, see if the large constant can be generated with 2 instructions. If not, load it from memory. default: // Is this a shifted 16b constant? If so, rewrite it to avoid a creating and loading a constant. val := p.From.Offset shift := bits.TrailingZeros64(uint64(val)) mask := int64(0xFFFF) << shift
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 18:17:17 UTC 2024 - 40.8K bytes - Viewed (0) -
src/cmd/internal/obj/ppc64/asm9.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 13:55:28 UTC 2024 - 156.1K bytes - Viewed (0)