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Results 1 - 10 of 15 for xmm (0.52 sec)
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src/cmd/asm/internal/lex/lex_test.go
"\n.\n.MOVBLZX.(.8.*.4.).(.R12.).,.AX.\n.ADDB.AX.,.DX.\n", }, { "nested multiline macro", lines( "#define KEYROUND(xmm, load, off, r1, r2, index) \\", "\tMOVBLZX (BP)(DX*4), R8 \\", "\tload((off+1), r2) \\", "\tMOVB R8, (off*4)(R12) \\", "\tPINSRW $index, (BP)(R8*4), xmm", "#define LOAD(off, reg) \\", "\tMOVBLZX (off*4)(R12), reg \\", "\tADDB reg, DX", "KEYROUND(X0, LOAD, 8, AX, BX, 0)",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Aug 29 07:48:38 UTC 2023 - 5.8K bytes - Viewed (0) -
src/internal/bytealg/equal_386.s
eq: MOVB $1, ret+8(FP) RET // a in SI // b in DI // count in BX // address of result byte in AX TEXT memeqbody<>(SB),NOSPLIT,$0-0 CMPL BX, $4 JB small // 64 bytes at a time using xmm registers hugeloop: CMPL BX, $64 JB bigloop #ifdef GO386_softfloat JMP bigloop #endif MOVOU (SI), X0 MOVOU (DI), X1 MOVOU 16(SI), X2 MOVOU 16(DI), X3 MOVOU 32(SI), X4 MOVOU 32(DI), X5
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Aug 23 21:22:58 UTC 2021 - 2.1K bytes - Viewed (0) -
src/internal/bytealg/equal_amd64.s
TEXT memeqbody<>(SB),NOSPLIT,$0-0 CMPQ BX, $8 JB small CMPQ BX, $64 JB bigloop #ifndef hasAVX2 CMPB internal∕cpu·X86+const_offsetX86HasAVX2(SB), $1 JE hugeloop_avx2 // 64 bytes at a time using xmm registers PCALIGN $16 hugeloop: CMPQ BX, $64 JB bigloop MOVOU (SI), X0 MOVOU (DI), X1 MOVOU 16(SI), X2 MOVOU 16(DI), X3 MOVOU 32(SI), X4 MOVOU 32(DI), X5 MOVOU 48(SI), X6 MOVOU 48(DI), X7
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Nov 17 16:34:40 UTC 2023 - 2.8K bytes - Viewed (0) -
src/vendor/golang.org/x/sys/cpu/cpu_x86.go
X86.HasRDRAND = isSet(30, ecx1) var osSupportsAVX, osSupportsAVX512 bool // For XGETBV, OSXSAVE bit is required and sufficient. if X86.HasOSXSAVE { eax, _ := xgetbv() // Check if XMM and YMM registers have OS support. osSupportsAVX = isSet(1, eax) && isSet(2, eax) if runtime.GOOS == "darwin" { // Darwin doesn't save/restore AVX-512 mask registers correctly across signal handlers.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 4.9K bytes - Viewed (0) -
src/vendor/golang.org/x/sys/cpu/cpu.go
// current X86/AMD64 platform. If the current platform // is not X86/AMD64 then all feature flags are false. // // X86 is padded to avoid false sharing. Further the HasAVX // and HasAVX2 are only set if the OS supports XMM and YMM // registers in addition to the CPUID feature bit being set. var X86 struct { _ CacheLinePad HasAES bool // AES hardware implementation (AES NI)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 08 16:12:58 UTC 2024 - 12.1K bytes - Viewed (0) -
src/internal/cpu/cpu_x86.go
osSupportsAVX := false osSupportsAVX512 := false // For XGETBV, OSXSAVE bit is required and sufficient. if X86.HasOSXSAVE { eax, _ := xgetbv() // Check if XMM and YMM registers have OS support. osSupportsAVX = isSet(eax, 1<<1) && isSet(eax, 1<<2) // AVX512 detection does not work on Darwin, // see https://github.com/golang/go/issues/49233 //
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 13:40:20 UTC 2024 - 5.8K bytes - Viewed (0) -
src/internal/chacha8rand/chacha8_amd64.s
SEED(1, SI, X5) SEED(2, R8, X6) SEED(3, R9, X7) SEED(4, R10, X8) SEED(5, R11, X9) SEED(6, R12, X10) SEED(7, R13, X11) // Zeros for remaining two matrix entries. // We have just enough XMM registers to hold the state, // without one for the temporary, so we flush and restore // some values to and from memory to provide a temporary. // The initial temporary is X15, so zero its memory instead // of X15 itself.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Dec 05 20:34:30 UTC 2023 - 4.6K bytes - Viewed (0) -
src/internal/cpu/cpu.go
var CacheLineSize uintptr = CacheLinePadSize // The booleans in X86 contain the correspondingly named cpuid feature bit. // HasAVX and HasAVX2 are only set if the OS does support XMM and YMM registers // in addition to the cpuid feature bit being set. // The struct is padded to avoid false sharing. var X86 struct { _ CacheLinePad HasAES bool HasADX bool HasAVX bool
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 15 19:57:43 UTC 2024 - 7.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/decode.go
xArgXmm // arg xmm xArgXMM0 // arg <XMM0> xArgXmm1 // arg xmm1 xArgXmm2 // arg xmm2 xArgXmm2M128 // arg xmm2/m128 xArgYmm2M256 // arg ymm2/m256 xArgXmm2M16 // arg xmm2/m16 xArgXmm2M32 // arg xmm2/m32 xArgXmm2M64 // arg xmm2/m64 xArgXmmM128 // arg xmm/m128 xArgXmmM32 // arg xmm/m32 xArgXmmM64 // arg xmm/m64
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 10 18:59:52 UTC 2023 - 45.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/inst.go
// 387 floating point registers. F0 F1 F2 F3 F4 F5 F6 F7 // MMX registers. M0 M1 M2 M3 M4 M5 M6 M7 // XMM registers. X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 // Segment registers. ES CS SS DS FS
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 10.6K bytes - Viewed (0)