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Results 1 - 10 of 88 for shift (0.03 sec)

  1. src/cmd/asm/internal/asm/testdata/arm64error.s

    	ADDS	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	ADDSW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	SUB	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    	SUBW	R7@>2, R5, R16                                   // ERROR "unsupported shift operator"
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 37.8K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/lex/lex.go

    	// a rune/ScanToken value for them - ugly but simple.
    	LSH          ScanToken = -1000 - iota // << Left shift.
    	RSH                                   // >> Logical right shift.
    	ARR                                   // -> Used on ARM for shift type 3, arithmetic right shift.
    	ROT                                   // @> Used on ARM for shift type 4, rotate right.
    	Include                               // included file started here
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Aug 29 18:31:05 UTC 2023
    - 4.1K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/expr_test.go

    	{"3%0", "modulo by zero"},
    	{"(1<<63)%0", "modulo of value with high bit set"},
    	{"3<<-4", "negative left shift count"},
    	{"3<<(1<<63)", "negative left shift count"},
    	{"3>>-4", "negative right shift count"},
    	{"3>>(1<<63)", "negative right shift count"},
    	{"(1<<63)>>2", "right shift of value with high bit set"},
    	{"(1<<62)>>2", ""},
    	{`'\x80'`, "illegal UTF-8 encoding for character constant"},
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Tue Aug 29 07:48:38 UTC 2023
    - 3.2K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/armerror.s

    	MOVB	R0>>8, R2          // ERROR "illegal shift"
    	MOVH	R0<<16, R2         // ERROR "illegal shift"
    	MOVBS	R0->8, R2          // ERROR "illegal shift"
    	MOVHS	R0<<24, R2         // ERROR "illegal shift"
    	MOVBU	R0->24, R2         // ERROR "illegal shift"
    	MOVHU	R0@>1, R2          // ERROR "illegal shift"
    	XTAB	R0>>8, R2          // ERROR "illegal shift"
    	XTAH	R0<<16, R2         // ERROR "illegal shift"
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Oct 23 15:18:14 UTC 2024
    - 14.5K bytes
    - Viewed (0)
  5. src/main/assemblies/files/fess

    do
        case $1 in
          --help) ARGV="$ARGV -h"; shift;;
          --*=*) properties="$properties -Dfess.${1#--}"
               shift 1
               ;;
          --*) [ $# -le 1 ] && {
                    echo "Option requires an argument: '$1'."
                    shift
                    continue
                }
               properties="$properties -Dfess.${1#--}=$2"
               shift 2
               ;;
          *) ARGV="$ARGV $1" ; shift
    Registered: Thu Oct 31 13:40:30 UTC 2024
    - Last Modified: Sun Jan 15 06:32:15 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  6. guava/src/com/google/common/hash/Murmur3_32HashFunction.java

            }
          }
    
          long buffer = 0;
          int shift = 0;
          for (; i < utf16Length; i++) {
            char c = input.charAt(i);
            if (c < 0x80) {
              buffer |= (long) c << shift;
              shift += 8;
              len++;
            } else if (c < 0x800) {
              buffer |= charToTwoUtf8Bytes(c) << shift;
              shift += 16;
              len += 2;
    Registered: Fri Nov 01 12:43:10 UTC 2024
    - Last Modified: Fri Aug 02 13:50:22 UTC 2024
    - 11.8K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/arch/arm64.go

    		}
    	}
    	return 0, false
    }
    
    // ARM64RegisterShift constructs an ARM64 register with shift operation.
    func ARM64RegisterShift(reg, op, count int16) (int64, error) {
    	// the base register of shift operations must be general register.
    	if reg > arm64.REG_R31 || reg < arm64.REG_R0 {
    		return 0, errors.New("invalid register for shift operation")
    	}
    	return int64(reg&31)<<16 | int64(op)<<22 | int64(uint16(count)), nil
    }
    
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Thu Sep 29 09:04:58 UTC 2022
    - 10.4K bytes
    - Viewed (0)
  8. okhttp-tls/src/main/kotlin/okhttp3/tls/internal/der/DerWriter.kt

        val sink = sink()
        val bitCount = 64 - java.lang.Long.numberOfLeadingZeros(v)
        val byteCount = (bitCount + 6) / 7
        for (shift in (byteCount - 1) * 7 downTo 0 step 7) {
          val lastBit = if (shift == 0) 0 else 0b1000_0000
          sink.writeByte(((v shr shift) and 0b0111_1111).toInt() or lastBit)
        }
      }
    
      override fun toString(): String = path.joinToString(separator = " / ")
    Registered: Fri Nov 01 11:42:11 UTC 2024
    - Last Modified: Mon Jan 08 01:13:22 UTC 2024
    - 5.7K bytes
    - Viewed (0)
  9. cmd/metacache-entries_test.go

    "src/compress/flate/testdata/huffman-rand-max.in", "src/compress/flate/testdata/huffman-shifts.dyn.expect", "src/compress/flate/testdata/huffman-shifts.dyn.expect-noinput", "src/compress/flate/testdata/huffman-shifts.golden", "src/compress/flate/testdata/huffman-shifts.in", "src/compress/flate/testdata/huffman-shifts.wb.expect", "src/compress/flate/testdata/huffman-shifts.wb.expect-noinput", "src/compress/flate/testdata/huffman-text-shift.dyn.expect", "src/compress/flate/testdata/huffman-text-shift.dyn.expect-noinput",...
    Registered: Sun Nov 03 19:28:11 UTC 2024
    - Last Modified: Sun Jan 02 17:15:06 UTC 2022
    - 31.6K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/parse.go

    			}
    		case lex.LSH:
    			p.next()
    			shift := p.factor()
    			if int64(shift) < 0 {
    				p.errorf("negative left shift count")
    			}
    			return value << shift
    		case lex.RSH:
    			p.next()
    			shift := p.term()
    			if int64(shift) < 0 {
    				p.errorf("negative right shift count")
    			}
    			if int64(value) < 0 {
    				p.errorf("right shift of value with high bit set")
    			}
    			value >>= shift
    Registered: Tue Nov 05 11:13:11 UTC 2024
    - Last Modified: Wed Sep 04 18:16:59 UTC 2024
    - 36.9K bytes
    - Viewed (0)
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