std::vector<const Node*>* body_nodes)
    TF_EXCLUSIVE_LOCKS_REQUIRED(fn_body->mu) {
  if (num_opers == -1) {
    for (const Node* node : fn_body->graph.op_nodes()) {
      const auto& iter = input_nodes.find(node);
      if (iter == input_nodes.end()) {
        // This node is not referenced in inputs. Add it to the body.
        body_nodes->push_back(node);
      } else {

def get_pr_nodes(settings: Settings) -> List[PullRequestNode]:
    pr_nodes: List[PullRequestNode] = []
    pr_edges = get_graphql_pr_edges(settings=settings)

    while pr_edges:
        for edge in pr_edges:
            pr_nodes.append(edge.node)
        last_edge = pr_edges[-1]
        pr_edges = get_graphql_pr_edges(settings=settings, after=last_edge.cursor)
    return pr_nodes


class ContributorsResults(BaseModel):

}

void TFE_GetExecutedOpNames(TFE_Context* ctx, TF_Buffer* buf,
                            TF_Status* status) {
  const std::vector<std::string>& op_names =
      tensorflow::unwrap(ctx)->GetLoggedOpsTestonly();

  std::ostringstream op_names_oss;
  for (const auto& op : op_names) {
    op_names_oss << op << ", ";
  }
  const std::string& op_names_str = op_names_oss.str();

	for i, s := range obj.Anames {
		instructions[s] = obj.As(i)
	}
	for i, s := range ppc64.Anames {
		if obj.As(i) >= obj.A_ARCHSPECIFIC {
			instructions[s] = obj.As(i) + obj.ABasePPC64
		}
	}
	// The opcodes generated by x/arch's ppc64map are listed in
	// a separate slice, add them too.
	for i, s := range ppc64.GenAnames {
		instructions[s] = obj.As(i) + ppc64.AFIRSTGEN
	}
	// Annoying aliases.

	XOR $1234567, R5, R3            // 6ca300126863d687
	XORIS $15, R3, R4               // 6c64000f
	XOR   $983040, R3, R4           // 6c64000f

	// TODO: cleanup inconsistency of printing CMPx opcodes with explicit CR arguments.
	CMP R3, R4                      // 7c232000
	CMP R3, R0                      // 7c230000
	CMP R3, R0, CR1                 // CMP R3,CR1,R0   // 7ca30000

<code>softfloat</code>) is made available to assembly code by predefining either
<code>GOMIPS64_hardfloat</code> or <code>GOMIPS64_softfloat</code>.
</p>

<h3 id="unsupported_opcodes">Unsupported opcodes</h3>

<p>
The assemblers are designed to support the compiler so not all hardware instructions
are defined for all architectures: if the compiler doesn't generate it, it might not be there.