assertEqualCharNodes(traverser.depthFirstPostOrder(charactersOf("bd")), "adcb");
    assertEqualCharNodes(traverser.depthFirstPostOrder(charactersOf("dc")), "cbad");
    assertEqualCharNodes(traverser.depthFirstPostOrder(charactersOf("bc")), "adcb");
  }

  @Test
  public void forGraph_depthFirstPostOrder_twoCycles() {

	V4FMADDPS (AX), [Z0-AX], K1, Z7  // ERROR "invalid instruction"
	// Usage of suffixes for non-EVEX instructions.
	ADCB.Z $7, AL                    // ERROR "invalid instruction"
	ADCB.RU_SAE $7, AL               // ERROR "invalid instruction"
	ADCB.RU_SAE.Z $7, AL             // ERROR "invalid instruction"
	// Usage of rounding with invalid operands.

ADCQ R11, R11 ADCQ R12, R12 ADCQ R13, R13 ADCQ CX, CX ADCQ $0x00, R15 // Missing products MOVQ (SI), AX MULQ AX MOVQ AX, R8 MOVQ DX, R14 MOVQ 8(SI), AX MULQ AX ADDQ R14, R9 ADCQ AX, R10 ADCQ $0x00, DX MOVQ DX, R14 MOVQ 16(SI), AX MULQ AX ADDQ R14, R11 ADCQ AX, R12 ADCQ $0x00, DX MOVQ DX, R14 MOVQ 24(SI), AX MULQ AX ADDQ R14, R13 ADCQ AX, CX ADCQ DX, R15 MOVQ R15, SI // First reduction step MOVQ R8, AX MOVQ R8, R15 SHLQ $0x20, R8 MULQ p256const1<>+0(SB) SHRQ $0x20, R15 ADDQ R8, R9 ADCQ R15, R10 ADCQ...

ADCQ R11, R11 ADCQ R12, R12 ADCQ R13, R13 ADCQ CX, CX ADCQ $0x00, R15 // Missing products MOVQ (SI), AX MULQ AX MOVQ AX, R8 MOVQ DX, R14 MOVQ 8(SI), AX MULQ AX ADDQ R14, R9 ADCQ AX, R10 ADCQ $0x00, DX MOVQ DX, R14 MOVQ 16(SI), AX MULQ AX ADDQ R14, R11 ADCQ AX, R12 ADCQ $0x00, DX MOVQ DX, R14 MOVQ 24(SI), AX MULQ AX ADDQ R14, R13 ADCQ AX, CX ADCQ DX, R15 MOVQ R15, SI // First reduction step MOVQ R8, AX MOVQ R8, R15 SHLQ $0x20, R8 MULQ p256const1<>+0(SB) SHRQ $0x20, R15 ADDQ R8, R9 ADCQ R15, R10 ADCQ...

	ADC	R0->28, R1           // 401ea1e0
	ADC	R0@>28, R1           // 601ea1e0
	ADC.S	R0<<28, R1           // 001eb1e0
	ADC.S	R0>>28, R1           // 201eb1e0
	ADC.S	R0->28, R1           // 401eb1e0
	ADC.S	R0@>28, R1           // 601eb1e0
	ADC	R0<<R1, R2, R3       // 1031a2e0
	ADC	R0>>R1, R2, R3       // 3031a2e0
	ADC	R0->R1, R2, R3       // 5031a2e0
	ADC	R0@>R1, R2, R3       // 7031a2e0

	},
	{
		"LOAD macro",
		lines(
			"#define LOAD(off, reg) \\",
			"\tMOVBLZX	(off*4)(R12),	reg \\",
			"\tADDB	reg,		DX",
			"",
			"LOAD(8, AX)",
		),
		"\n.\n.MOVBLZX.(.8.*.4.).(.R12.).,.AX.\n.ADDB.AX.,.DX.\n",
	},
	{
		"nested multiline macro",
		lines(
			"#define KEYROUND(xmm, load, off, r1, r2, index) \\",
			"\tMOVBLZX	(BP)(DX*4),	R8 \\",
			"\tload((off+1), r2) \\",

  },
  {
    "comment": "IDNA ignored code points",
    "input": "a\u00ADb",
    "output": "ab"
  },
  {
    "input": "a%C2%ADb",
    "output": "ab"
  },
  {
    "comment": "Empty host after domain to ASCII",
    "input": "\u00AD",
    "output": null
  },
  {
    "input": "%C2%AD",
    "output": null
  },
  {

TEXT asmtest(SB),DUPOK|NOSPLIT,$-8

	AND $(1<<63), R1                           // AND $-9223372036854775808, R1     // 21004192
	ADCW ZR, R8, R10                           // 0a011f1a
	ADC R0, R2, R12                            // 4c00009a
	ADCSW R9, R21, R6                          // a602093a
	ADCS R23, R22, R22                         // d60217ba
	ADDW R5.UXTH, R8, R9                       // 0921250b

    <inspection_tool class="21f28a86-2ba8-3048-9ce1-b6f10d4d4a12" enabled="true" level="WEAK WARNING" enabled_by_default="true" editorAttributes="INFO_ATTRIBUTES" />
    <inspection_tool class="73cd39e8-e54e-3a38-ad1b-b883fff4b1eb" enabled="true" level="WEAK WARNING" enabled_by_default="true" editorAttributes="INFO_ATTRIBUTES" />
    <inspection_tool class="AsciiDocLinkResolve" enabled="false" level="ERROR" enabled_by_default="false" />

        }
    }

    @Nested
    @DisplayName("Constants Tests")
    class ConstantsTests {

        @Test
        @DisplayName("Should define correct ACB (Account Control Block) constants")
        void testACBConstants() {
            // Verify all ACB constants
            assertEquals(1, samr.ACB_DISABLED);
            assertEquals(2, samr.ACB_HOMDIRREQ);
            assertEquals(4, samr.ACB_PWNOTREQ);