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Results 1 - 10 of 12 for R15 (0.42 sec)

  1. src/cmd/asm/internal/asm/testdata/mips64.s

    //	LMOVB rreg ',' addr
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	MOVB	R1, foo<>+3(SB)
    	MOVB	R5, -18(R4)	// a085ffee
    	MOVB	R10, 9(R13)	// a1aa0009
    	MOVB	R15, (R13)	// a1af0000
    	MOVBU	R5, -18(R4)	// a085ffee
    	MOVBU	R10, 9(R13)	// a1aa0009
    	MOVBU	R15, (R13)	// a1af0000
    
    //
    // store floats
    //
    //	LMOVW freg ',' addr
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	MOVD	F1, foo<>+3(SB)
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/asm/testdata/s390x.s

    	MOVD	(R15), R1             // e310f0000004
    	MOVW	(R15), R2             // e320f0000014
    	MOVH	(R15), R3             // e330f0000015
    	MOVB	(R15), R4             // e340f0000077
    	MOVWZ	(R15), R5             // e350f0000016
    	MOVHZ	(R15), R6             // e360f0000091
    	MOVBZ	(R15), R7             // e370f0000090
    	MOVDBR	(R15), R8             // e380f000000f
    	MOVWBR	(R15), R9             // e390f000001e
    
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Jul 30 19:29:15 UTC 2025
    - 22.9K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s

    	XORQ R15, R15
    	RET
    TEXT ·a5(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	XORL R15, R15
    	RET
    TEXT ·a6(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	POPQ R15
    	PUSHQ R15
    	RET
    TEXT ·a7(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    	MOVQ R15, AX // ERROR "when dynamic linking, R15 is clobbered by a global variable access and is used here"
    	RET
    TEXT ·a8(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 15 20:45:41 UTC 2023
    - 4.8K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/amd64enc_extra.s

    	VGATHERDPD 360(R15)(Y30*2), K6, Z20 // 6282fd469264772d
    	VGATHERDPD 640(R15)(Y20*2), K6, Z10 // 6252fd4692546750
    	VGATHERDPD 960(R15)(Y10*2), K6, Z20 // 6282fd4e92645778
    	VGATHERDPD 1280(R15)(Y0*2), K6, Z10 // 6252fd4e92944700050000
    	VGATHERDPS 360(R15)(X30*2), K6, X20 // 62827d069264775a
    	VGATHERDPS 640(R15)(X20*2), K6, X10 // 62527d0692946780020000
    	VGATHERDPS 960(R15)(X10*2), K6, X20 // 62827d0e92a457c0030000
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Thu Feb 20 11:20:03 UTC 2025
    - 57.7K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/operand_test.go

    	{"R11", "R11"},
    	{"R12", "R12"},
    	{"R13", "R13"},
    	{"R14", "R14"},
    	{"R15", "R15"},
    	{"R1<<2(R3)", "R1<<2(R3)"},
    	{"R(1)<<2(R(3))", "R1<<2(R3)"},
    	{"R2", "R2"},
    	{"R3", "R3"},
    	{"R4", "R4"},
    	{"R(4)", "R4"},
    	{"R5", "R5"},
    	{"R6", "R6"},
    	{"R7", "R7"},
    	{"R8", "R8"},
    	{"[R0,R1,g,R15]", "[R0,R1,g,R15]"},
    	{"[R0-R7]", "[R0,R1,R2,R3,R4,R5,R6,R7]"},
    	{"[R(0)-R(7)]", "[R0,R1,R2,R3,R4,R5,R6,R7]"},
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Tue Aug 29 18:31:05 UTC 2023
    - 23.9K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/arm64enc.s

    	CLREX $0                                   // 5f3003d5
    	CLSW R15, R6                               // e615c05a
    	CLS R15, ZR                                // ff15c0da
    	CLZW R1, R14                               // 2e10c05a
    	CLZ R21, R9                                // a912c0da
    	CMNW R21.UXTB<<4, R15                      // ff11352b
    	CMN R0.UXTW<<4, R16                        // 1f5220ab
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Mon Jul 24 01:11:41 UTC 2023
    - 43.9K bytes
    - Viewed (0)
  7. lib/fips140/v1.0.0.zip

    ADDQ R8, R9 ADCQ R15, R10 ADCQ AX, R11 ADCQ DX, R12 XORQ R13, R13 // Second stage MOVQ R9, AX MOVQ R9, R15 SHLQ $0x20, R9 MULQ p256const1<>+0(SB) SHRQ $0x20, R15 ADDQ R9, R10 ADCQ R15, R11 ADCQ AX, R12 ADCQ DX, R13 XORQ R8, R8 // Third stage MOVQ R10, AX MOVQ R10, R15 SHLQ $0x20, R10 MULQ p256const1<>+0(SB) SHRQ $0x20, R15 ADDQ R10, R11 ADCQ R15, R12 ADCQ AX, R13 ADCQ DX, R8 XORQ R9, R9 // Last stage MOVQ R11, AX MOVQ R11, R15 SHLQ $0x20, R11 MULQ p256const1<>+0(SB) SHRQ $0x20, R15 ADDQ R11, R12 ADCQ...
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Jan 29 15:10:35 UTC 2025
    - 635K bytes
    - Viewed (0)
  8. src/cmd/asm/internal/asm/testdata/arm64.s

    	VLD1R.P	(R15)(R1), [V15.H4]                             // efc5c10d
    	VLD2R	(R15), [V15.H4, V16.H4]                         // efc5600d
    	VLD2R.P	16(R0), [V0.D2, V1.D2]                          // 00ccff4d
    	VLD2R.P	(R0)(R5), [V31.D1, V0.D1]                       // 1fcce50d
    	VLD3R	(RSP), [V31.S2, V0.S2, V1.S2]                   // ffeb400d
    	VLD3R.P	6(R15), [V15.H4, V16.H4, V17.H4]                // efe5df0d
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Wed Mar 26 10:48:50 UTC 2025
    - 95.3K bytes
    - Viewed (0)
  9. src/test/java/jcifs/smb/NtlmUtilTest.java

            // Act
            byte[] r14 = NtlmUtil.getPreNTLMResponse(cifsContext, password14, challenge);
            byte[] r15 = NtlmUtil.getPreNTLMResponse(cifsContext, password15, challenge);
    
            // Assert: equal because only first 14 OEM bytes are used
            assertArrayEquals(r14, r15, "Only first 14 OEM bytes affect Pre-NTLM response");
            assertEquals(24, r14.length);
    
            // Verify collaborator interactions
    Registered: Sun Sep 07 00:10:21 UTC 2025
    - Last Modified: Sat Aug 30 05:58:03 UTC 2025
    - 12K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/parse.go

    	}
    	if name[0] != 'R' {
    		p.errorf("expected g or R0 through R15; found %s", name)
    		return 0
    	}
    	r, ok := p.registerReference(name)
    	if !ok {
    		return 0
    	}
    	reg := r - p.arch.Register["R0"]
    	if reg < 0 {
    		// Could happen for an architecture having other registers prefixed by R
    		p.errorf("expected g or R0 through R15; found %s", name)
    		return 0
    	}
    	return uint16(reg)
    }
    
    Registered: Tue Sep 09 11:13:09 UTC 2025
    - Last Modified: Fri Feb 14 15:13:11 UTC 2025
    - 37.3K bytes
    - Viewed (0)
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