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Results 1 - 10 of 150 for 64xf32 (0.08 sec)
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tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_gpu_cc_60.mlir
exponential_avg_factor = 1.0 : f32, is_training = true } : (tensor<1x28x28x64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) -> (tensor<1x28x28x64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) func.return %y : tensor<1x28x28x64xf32> } // CHECK-LABEL: func @transposeFusedBatchNormV3_f16
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 21 08:41:18 UTC 2022 - 5.8K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/tpu-merge-variables-with-execute.mlir
Targs = [tensor<32xf32>, tensor<64xf32>, tensor<8xf32>, tensor<2xf32>], Tresults = [tensor<32xf32>, tensor<64xf32>, tensor<8xf32>]} : (tensor<32xf32>, tensor<64xf32>, tensor<8xf32>, tensor<2xf32>, tensor<2x!tf_type.string>) -> (tensor<32xf32>, tensor<64xf32>, tensor<8xf32>) tf_device.return %0#0, %0#1, %0#2 : tensor<32xf32>, tensor<64xf32>, tensor<8xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Oct 31 08:59:10 UTC 2023 - 24.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/compile_mlir_util/shape-inference-after-legalization.mlir
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Wed Mar 23 18:56:13 UTC 2022 - 1.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_gpu_cc_70.mlir
exponential_avg_factor = 1.0 : f32, is_training = true } : (tensor<1x28x28x64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) -> (tensor<1x28x28x64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) func.return %y : tensor<1x28x28x64xf32> } // CHECK-LABEL: func @transposeFusedBatchNormV3_f16
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 21 08:41:18 UTC 2022 - 8.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_to_nhwc.mlir
data_format = "NCHW", epsilon = 1.001000e-05 : f32, is_training = false } : (tensor<?x64x112x112xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) -> (tensor<?x64x112x112xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<*xf32>) // CHECK: "tf.FusedBatchNormV3" // CHECK-SAME: data_format = "NHWC"
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 7.3K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nchw.mlir
exponential_avg_factor = 1.0 : f32, is_training = true } : (tensor<1x28x28x64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) -> (tensor<1x28x28x64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) func.return %y : tensor<1x28x28x64xf32> } // CHECK-LABEL: func @transposeFusedBatchNormGradV3
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 9K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_layout_assignment_to_nhwc.mlir
exponential_avg_factor = 1.0 : f32, is_training = true } : (tensor<1x64x28x28xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) -> (tensor<1x64x28x28xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) func.return %y : tensor<1x64x28x28xf32> } // CHECK-LABEL: bias_add_nchw
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 4.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/tensorflow/tests/layout_optimization_move_transposes_end.mlir
exponential_avg_factor = 1.0 : f32, is_training = false } : (tensor<1x112x112x64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) -> (tensor<1x112x112x64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>, tensor<64xf32>) func.return %2#0 : tensor<1x112x112x64xf32> } // CHECK-LABEL: func @fold_into_pad_with_extra_uses
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Oct 30 06:52:55 UTC 2023 - 9.5K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/quantize-dynamic-range.mlir
%b = arith.constant dense<-1.23697901> : tensor<64xf32> %conv = "tfl.conv_2d"(%arg0, %w, %b) {dilation_h_factor = 1 : i32, dilation_w_factor = 1 : i32, fused_activation_function = "NONE", padding = "SAME", stride_h = 2 : i32, stride_w = 2 : i32} : (tensor<1x224x224x3xf32>, tensor<64x3x3x3xf32>, tensor<64xf32>) -> tensor<1x112x112x64xf32> func.return %conv : tensor<1x112x112x64xf32>
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 23 21:09:00 UTC 2024 - 23.2K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/tests/canonicalize.mlir
%0 = "tfl.reshape"(%arg0, %shape0) : (tensor<4x4x4xf32>, tensor<2xi32>) -> tensor<16x4xf32> %1 = "tfl.reshape"(%0, %shape1) : (tensor<16x4xf32>, tensor<1xi32>) -> tensor<64xf32> %2 = "tfl.reshape"(%0, %shape1) : (tensor<16x4xf32>, tensor<1xi32>) -> tensor<64xf32> %3 = arith.addf %1, %2 : tensor<64xf32> func.return %3 : tensor<64xf32> // CHECK-LABEL: func @reshape_removeAdjacentWithMultipleUse
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Thu May 02 09:41:17 UTC 2024 - 20.6K bytes - Viewed (0)