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Results 1 - 4 of 4 for v12 (0.04 sec)

  2. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/arm64error.s 

    	VMOV	V8.D[0], V12.S[1]                                // ERROR "operand mismatch"
	VMOV	V8.D[0], V12.H[1]                                // ERROR "operand mismatch"
	VMOV	V8.D[0], V12.B[1]                                // ERROR "operand mismatch"
	VMOV	V8.S[0], V12.H[1]                                // ERROR "operand mismatch"
	VMOV	V8.S[0], V12.B[1]                                // ERROR "operand mismatch"
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Tue Oct 14 19:00:00 UTC 2025
    - 38.4K bytes
    - Viewed (0)
  3. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/arm64.s 

    	VADD	V1, V3, V3                      // 6384e15e
	VSUB	V12, V30, V30                   // de87ec7e
	VSUB	V12, V20, V30                   // 9e86ec7e
	VFMLA	V1.D2, V12.D2, V1.D2            // 81cd614e
	VFMLA	V1.S2, V12.S2, V1.S2            // 81cd210e
	VFMLA	V1.S4, V12.S4, V1.S4            // 81cd214e
	VFMLS	V1.D2, V12.D2, V1.D2            // 81cde14e
	VFMLS	V1.S2, V12.S2, V1.S2            // 81cda10e
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Mon Nov 10 17:34:13 UTC 2025
    - 96.1K bytes
    - Viewed (0)
  4. github.com/golang/go

    lib/fips140/v1.1.0-rc1.zip 

    V11.B16, V7.B16 AESMC V7.B16, V7.B16 Lenc128: VLD1.P 64(XK), [V12.B16, V13.B16, V14.B16, V15.B16] VLD1.P 64(XK), [V16.B16, V17.B16, V18.B16, V19.B16] VLD1.P 48(XK), [V20.B16, V21.B16, V22.B16] AESE V12.B16, V0.B16 AESMC V0.B16, V0.B16 AESE V12.B16, V1.B16 AESMC V1.B16, V1.B16 AESE V12.B16, V2.B16 AESMC V2.B16, V2.B16 AESE V12.B16, V3.B16 AESMC V3.B16, V3.B16 AESE V12.B16, V4.B16 AESMC V4.B16, V4.B16 AESE V12.B16, V5.B16 AESMC V5.B16, V5.B16 AESE V12.B16, V6.B16 AESMC V6.B16, V6.B16 AESE V12.B16, V7.B16 AESMC...
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Dec 11 16:27:41 UTC 2025
    - 663K bytes
    - Viewed (0)
  5. github.com/golang/go

    src/cmd/asm/internal/asm/testdata/riscv64.s 

    	VRGATHERVI	$16, V2, V0, V3			// d7312830

	// 31.16.5: Vector Compress Instruction
	VCOMPRESSVM	V1, V2, V3			// d7a1205e

	// 31.16.6: Whole Vector Register Move
	VMV1RV		V2, V1				// d730209e
	VMV2RV		V12, V10			// 57b5c09e
	VMV4RV		V8, V4				// 57b2819e
	VMV8RV		V8, V0				// 57b0839e

	//
	// Privileged ISA
	//

	// 3.3.1: Environment Call and Breakpoint
	ECALL						// 73000000
    Registered: Tue Dec 30 11:13:12 UTC 2025
    - Last Modified: Thu Nov 13 12:17:37 UTC 2025
    - 73.7K bytes
    - Viewed (0)
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