- Sort Score
- Result 10 results
- Languages All
Results 1 - 7 of 7 for riscv64 (0.06 sec)
-
src/cmd/asm/internal/asm/testdata/riscv64.s
Joel Sing <******@****.***> 1757427420 +1000
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 73.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/endtoend_test.go
defer func(orig int) { buildcfg.GORISCV64 = orig }(buildcfg.GORISCV64) for _, goriscv64 := range []int{20, 22, 23} { t.Run(fmt.Sprintf("rva%vu64", goriscv64), func(t *testing.T) { buildcfg.GORISCV64 = goriscv64 testFn(t) }) } } func TestRISCV64EndToEnd(t *testing.T) { testRISCV64AllProfiles(t, func(t *testing.T) { testEndToEnd(t, "riscv64", "riscv64") }) }
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Tue Dec 23 18:45:48 UTC 2025 - 12.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/asm.go
// passed RestArgs/AddRestSource switch a[1].Type { case obj.TYPE_REG: prog.Reg = p.getRegister(prog, op, &a[1]) default: prog.AddRestSource(a[1]) } case sys.RISCV64: // RISCV64 instructions with one input and two outputs. if arch.IsRISCV64AMO(op) { prog.From = a[0] prog.To = a[1] if a[2].Type != obj.TYPE_REG {Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Tue Oct 21 15:13:08 UTC 2025 - 26.7K bytes - Viewed (0) -
doc/asm.html
<code>softfloat</code>) is made available to assembly code by predefining either <code>GOMIPS64_hardfloat</code> or <code>GOMIPS64_softfloat</code>. </p> <h3 id="riscv64">RISCV64</h3> <p> Reference: <a href="/pkg/cmd/internal/obj/riscv">Go RISCV64 Assembly Instructions Reference Manual</a> </p> <h3 id="unsupported_opcodes">Unsupported opcodes</h3> <p>
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Fri Nov 14 19:09:46 UTC 2025 - 36.5K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arch.go
register["TP"] = riscv.REG_TP register["T0"] = riscv.REG_T0 register["T1"] = riscv.REG_T1 register["T2"] = riscv.REG_T2 register["S0"] = riscv.REG_S0 register["S1"] = riscv.REG_S1 register["A0"] = riscv.REG_A0 register["A1"] = riscv.REG_A1 register["A2"] = riscv.REG_A2 register["A3"] = riscv.REG_A3 register["A4"] = riscv.REG_A4 register["A5"] = riscv.REG_A5 register["A6"] = riscv.REG_A6
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 21.7K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
} for { tok = p.nextToken() if len(operands) == 0 && len(items) == 0 { if p.arch.InFamily(sys.ARM, sys.ARM64, sys.AMD64, sys.I386, sys.Loong64, sys.RISCV64) && tok == '.' { // Suffixes: ARM conditionals, Loong64 vector instructions, RISCV rounding mode or x86 modifiers. tok = p.nextToken() str := p.lex.Text() if tok != scanner.Ident {Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Wed Nov 12 03:59:40 UTC 2025 - 37.3K bytes - Viewed (0) -
lib/fips140/v1.1.0-rc1.zip
file. //go:build (amd64 || arm64 || ppc64 || ppc64le || riscv64) && !purego package subtle //go:noescape func xorBytes(dst, a, b *byte, n int) golang.org/fips140@v1.1.0-rc1/fips140/v1.1.0-rc1/subtle/xor_generic.go // Copyright 2013 The Go Authors. All rights reserved. // Use of this source code is governed by a BSD-style // license that can be found in the LICENSE file. //go:build (!amd64 && !arm64 && !loong64 && !ppc64 && !ppc64le && !riscv64) || purego package subtle import ( "runtime" "unsafe" )...
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Dec 11 16:27:41 UTC 2025 - 663K bytes - Viewed (0)