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Results 1 - 10 of 34 for intconst (0.16 sec)
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src/cmd/compile/internal/rangefunc/rewrite.go
var thenList []syntax.Stmt if zeroNext { clr := &syntax.AssignStmt{ Lhs: r.next(), Rhs: r.intConst(0), } thenList = append(thenList, clr) } for _, then := range thens { thenList = append(thenList, then) } nif := &syntax.IfStmt{ Cond: r.cond(op, r.next(), r.intConst(c)), Then: &syntax.BlockStmt{ List: thenList, }, } return nif }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 01:05:44 UTC 2024 - 41.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
(ANDconst [c] (MOVDconst [d])) => (MOVDconst [c&d]) (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x) (ANDconst [c] (MOVWUreg x)) => (ANDconst [c&(1<<32-1)] x) (ANDconst [c] (MOVHUreg x)) => (ANDconst [c&(1<<16-1)] x) (ANDconst [c] (MOVBUreg x)) => (ANDconst [c&(1<<8-1)] x) (MOVWUreg (ANDconst [c] x)) => (ANDconst [c&(1<<32-1)] x) (MOVHUreg (ANDconst [c] x)) => (ANDconst [c&(1<<16-1)] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64.rules
(AND x (MOVDconst [c])) && isU16Bit(c) => (ANDconst [c] x) (XOR x (MOVDconst [c])) && isU32Bit(c) => (XORconst [c] x) (OR x (MOVDconst [c])) && isU32Bit(c) => (ORconst [c] x) // Simplify consts (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x) (ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x) (XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x) (ANDconst [-1] x) => x (ANDconst [0] _) => (MOVDconst [0]) (XORconst [0] x) => x
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 53.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64latelower.rules
(CMPconst [0] z:(ANDconst [c] x)) && int64(uint16(c)) == c && v.Block == z.Block => (CMPconst [0] convertPPC64OpToOpCC(z)) // And finally, fixup the flag user. (CMPconst <t> [0] (Select0 z:((ADD|AND|ANDN|OR|SUB|NOR|XOR)CC x y))) => (Select1 <t> z) (CMPconst <t> [0] (Select0 z:((ADDCCconst|ANDCCconst|NEGCC|CNTLZDCC|RLDICLCC) y))) => (Select1 <t> z)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 3.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64.go
return true } // match: (ANDconst [c] (MOVDconst [d])) // result: (MOVDconst [c&d]) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpARM64MOVDconst { break } d := auxIntToInt64(v_0.AuxInt) v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(c & d) return true } // match: (ANDconst [c] (ANDconst [d] x)) // result: (ANDconst [c&d] x) for {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 608.6K bytes - Viewed (0) -
tensorflow/compiler/mlir/lite/experimental/tac/execution_metadata_exporter.cc
#include "tensorflow/compiler/mlir/lite/ir/tfl_ops.h" #include "tensorflow/compiler/mlir/lite/quantization/ir/QuantOps.h" #include "tensorflow/compiler/mlir/tensorflow/ir/tf_ops.h" namespace tflite { namespace { bool IsConst(mlir::Operation* op) { return llvm::isa<mlir::arith::ConstantOp, mlir::TF::ConstOp, mlir::TFL::ConstOp, mlir::TFL::QConstOp>(op); } bool IsOpSupported(mlir::Operation* op, const std::string& hardware) {
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Tue Jun 11 06:11:34 UTC 2024 - 7.5K bytes - Viewed (0) -
analysis/analysis-api-fe10/src/org/jetbrains/kotlin/analysis/api/descriptors/symbols/descriptorBased/KtFe10DescKotlinPropertySymbol.kt
} descriptor.ktSymbolKind } override val isLateInit: Boolean get() = withValidityAssertion { descriptor.isLateInit } override val isConst: Boolean get() = withValidityAssertion { descriptor.isConst } override val isVal: Boolean get() = withValidityAssertion { !descriptor.isVar } override val isExtension: Boolean
Registered: Wed Jun 12 09:53:16 UTC 2024 - Last Modified: Mon May 27 09:59:11 UTC 2024 - 6.2K bytes - Viewed (0) -
analysis/analysis-api-fir/src/org/jetbrains/kotlin/analysis/api/fir/symbols/KtFirKotlinPropertySymbol.kt
} override val isOverride: Boolean get() = withValidityAssertion { firSymbol.isOverride } override val isConst: Boolean get() = withValidityAssertion { firSymbol.isConst } override val isStatic: Boolean get() = withValidityAssertion { firSymbol.isStatic } override val isActual: Boolean get() = withValidityAssertion { firSymbol.isActual }
Registered: Wed Jun 12 09:53:16 UTC 2024 - Last Modified: Tue Jun 11 15:45:42 UTC 2024 - 7.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewritePPC64.go
return true } // match: (ANDconst [c] (ANDconst [d] x)) // result: (ANDconst [c&d] x) for { c := auxIntToInt64(v.AuxInt) if v_0.Op != OpPPC64ANDconst { break } d := auxIntToInt64(v_0.AuxInt) x := v_0.Args[0] v.reset(OpPPC64ANDconst) v.AuxInt = int64ToAuxInt(c & d) v.AddArg(x) return true } // match: (ANDconst [-1] x) // result: x for {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 19:02:52 UTC 2024 - 360.2K bytes - Viewed (0) -
analysis/analysis-api/src/org/jetbrains/kotlin/analysis/api/renderer/declarations/modifiers/renderers/KtRendererOtherModifiersProvider.kt
Registered: Wed Jun 12 09:53:16 UTC 2024 - Last Modified: Wed May 22 06:28:34 UTC 2024 - 4.4K bytes - Viewed (0)