*/
    @Test
    void testBuildFromMiddlePom() throws Exception {
        File f1 = getTestFile("src/test/resources/projects/grandchild-check/child/pom.xml");
        File f2 = getTestFile("src/test/resources/projects/grandchild-check/child/grandchild/pom.xml");

        getProject(f1);

        // it's the building of the grandchild project, having already cached the child project

	MOVD	R1, 0x44332211(R2)	// MOVD		R1, 1144201745(R2)
	FMOVS	F1, 0x1003000(R2)	// FMOVS	F1, 16789504(R2)
	FMOVS	F1, 0x44332211(R2)	// FMOVS	F1, 1144201745(R2)
	FMOVD	F1, 0x1007000(R2)	// FMOVD	F1, 16805888(R2)
	FMOVD	F1, 0x44332211(R2)	// FMOVD	F1, 1144201745(R2)
	FMOVQ	F1, 0x1003000(R2)	// FMOVQ	F1, 16789504(R2)
	FMOVQ	F1, 0x44332211(R2)	// FMOVQ	F1, 1144201745(R2)

	MOVB	0x1000000(R1), R2	// MOVB		16777216(R1), R2

	FCVTDLU X5, F0					// 538032d2
	FCVTSD	F0, F1					// d3001040
	FCVTDS	F0, F1					// d3000042
	FSGNJD	F1, F0, F2				// 53011022
	FSGNJND	F1, F0, F2				// 53111022
	FSGNJXD	F1, F0, F2				// 53211022
	FMVXD	F0, X5					// d30200e2
	FMVDX	X5, F0					// 538002f2
	FMADDD	F1, F2, F3, F4				// 4382201a
	FMSUBD	F1, F2, F3, F4				// 4782201a
	FNMSUBD	F1, F2, F3, F4				// 4b82201a
	FNMADDD	F1, F2, F3, F4				// 4f82201a

	FCLASSF		F4, F5		// 85341401
	FCLASSD		F4, F5		// 85381401

	FFINTFW		F0, F1		// 01101d01
	FFINTFV		F0, F1		// 01181d01
	FFINTDW		F0, F1		// 01201d01
	FFINTDV		F0, F1		// 01281d01
	FTINTWF		F0, F1		// 01041b01
	FTINTWD		F0, F1		// 01081b01
	FTINTVF		F0, F1		// 01241b01
	FTINTVD		F0, F1		// 01281b01

	FMAXAF		F4, F5, F6	// a6900c01
	FMAXAF		F4, F5		// a5900c01

// the validate function from being run and TestRISCVValidation will report missing
// errors.

TEXT validation(SB),$0
	SRLI	$1, X5, F1			// ERROR "expected integer register in rd position but got non-integer register F1"
	SRLI	$1, F1, X5			// ERROR "expected integer register in rs1 position but got non-integer register F1"

	WORD	$-1				// ERROR "must be in range [0x0, 0xffffffff]"
	WORD	$0x100000000			// ERROR "must be in range [0x0, 0xffffffff]"

0000070 2e 4c 6e a5 60 45 02 62 81 95 b6 94 9e 9e 77 e7
0000080 d0 43 b6 f8 71 df 96 3c e7 a4 69 ce bf cf e9 79
0000090 ce ef 79 3f bf f1 31 db b6 bb 31 76 92 e7 f3 07
00000a0 8b fc 9c ca cc 08 cc cb cc 5e d2 1c 88 d9 7e bb
00000b0 4f bb 3a 3f 75 f1 5d 7f 8f c2 68 67 77 8f 25 ff
00000c0 84 e2 93 2d ef a4 95 3d 71 4e 2c b9 b0 87 c3 be
00000d0 3d f8 a7 60 24 61 c5 ef ae 9e c8 6c 6d 4e 69 c8

	LDP.W	8(R3), (R2, R3)                                  // ERROR "constrained unpredictable behavior"
	LDP	(R1), (R2, R2)                                   // ERROR "constrained unpredictable behavior"
	LDP	(R0), (F0, F1)                                   // ERROR "invalid register pair"
	LDXPW	(RSP), (R2, R2)                                  // ERROR "constrained unpredictable behavior"

  EXPECT_EQ(op_def.output_arg_size(), 1);
  EXPECT_TRUE(op_def.is_stateful());

  TF_DeleteBuffer(buffer);
}

void AssertEqual(TF_Function* f1, TF_Function* f2) {
  string s1, s2;
  tensorflow::FunctionDef fdef1, fdef2;
  ASSERT_TRUE(GetFunctionDef(f1, &fdef1));
  ASSERT_TRUE(GetFunctionDef(f2, &fdef2));
  SerializeToStringDeterministic(fdef1, &s1);
  SerializeToStringDeterministic(fdef2, &s2);

}

// invalid: 1e3 is a floating-point constant
for range 1e3 {
}

// fibo generates the Fibonacci sequence
fibo := func(yield func(x int) bool) {
	f0, f1 := 0, 1
	for yield(f0) {
		f0, f1 = f1, f0+f1
	}
}

// print the Fibonacci numbers below 1000:
for x := range fibo {
	if x >= 1000 {
		break
	}
	fmt.Printf("%d ", x)
}

t.Errorf("wrong answer: %d + %d*(2**64)", r.lo, r.hi) } } func TestSetBytesRoundTri(t *testing.T) { f1 := func(in [32]byte, fe Element) bool { fe.SetBytes(in[:]) // Mask the most significant bit as it's ignored by SetBytes. (Now // instead of earlier so we check the masking in SetBytes is working.) in[len(in)-1] &= (1 << 7) - 1 return bytes.Equal(in[:], fe.Bytes()) && isInBounds(&fe) } if err := quick.Check(f1, nil); err != nil { t.Errorf("failed bytes->FE->bytes round-trip: %v", err) } f2 := func(fe, r...