DARN $1, R5                     // 7ca105e6

	DCBF (R3)(R4)                   // 7c0418ac
	DCBF (R3)(R0)                   // 7c0018ac
	DCBF (R3)                       // 7c0018ac

	DCBST (R3)(R4)                  // 7c04186c
	DCBST (R3)(R0)                  // 7c00186c
	DCBST (R3)                      // 7c00186c
	DCBZ (R3)(R4)                   // 7c041fec
	DCBZ (R3)(R0)                   // 7c001fec

	{as: ATW, a1: C_32CON, a2: C_REG, a6: C_S16CON, type_: 61, size: 4},
	{as: ADCBF, a1: C_SOREG, type_: 43, size: 4},
	{as: ADCBF, a1: C_XOREG, type_: 43, size: 4},
	{as: ADCBF, a1: C_XOREG, a2: C_REG, a6: C_U15CON, type_: 43, size: 4},
	{as: ADCBF, a1: C_SOREG, a6: C_U15CON, type_: 43, size: 4},
	{as: ADCBF, a1: C_XOREG, a6: C_U15CON, type_: 43, size: 4},

    - andrewsykim
    - aojea
    - bowei
    - caseydavenport
    - danwinship
    - dcbw
    - freehan
    - khenidak
    - mrhohn
    - robscott
    - thockin
  sig-network-reviewers:
    - andrewsykim
    - aojea
    - aroradaman
    - bowei
    - caseydavenport
    - danwinship
    - dcbw
    - freehan
    - khenidak
    - mrhohn
    - robscott
    - thockin
    - tnqn

	ADDC  R20, R4, R6	// R6 = x[i] + c
	CMP   R11, $0		// If z_len was 1, we are done
	MOVD  R6, 0(R10)	// z[i]
	BEQ   final

	// We will read 4 elements per iteration
	SRDCC $2, R11, R9	// R9 = z_len/4
	DCBT  (R8)
	MOVD  R9, CTR		// Set up the loop counter
	BEQ   tail		// If R9 = 0, we can't use the loop
	PCALIGN $16

loop:
	MOVD  8(R8), R20	// R20 = x[i]
	MOVD  16(R8), R21	// R21 = x[i+1]

// Prefetch instructions (TH specified using aux field)
// For DCBT Ra,Rb,TH, A value of TH indicates:
//     0, hint this cache line will be used soon. (PrefetchCache)
//     16, hint this cache line will not be used for long. (PrefetchCacheStreamed)
// See ISA 3.0 Book II 4.3.2 for more detail. https://openpower.foundation/specifications/isa/
(PrefetchCache ptr mem)          => (DCBT ptr mem [0])
(PrefetchCacheStreamed ptr mem)  => (DCBT ptr mem [16])

		// Prefetch instruction
		// Do prefetch of address generated with arg0 and arg1 with option aux. arg0=addr,arg1=memory, aux=option.
		{name: "DCBT", argLength: 2, aux: "Int64", reg: prefreg, asm: "DCBT", hasSideEffects: true},

		// Store bytes in the reverse endian order of the arch into arg0.
		// These are indexed stores with no offset field in the instruction so the auxint fields are not used.

		case ALWAR,
			ALBAR,
			ASTBCCC,
			ASTWCCC,
			AEIEIO,
			AICBI,
			AISYNC,
			ATLBIE,
			ATLBIEL,
			ASLBIA,
			ASLBIE,
			ASLBMFEE,
			ASLBMFEV,
			ASLBMTE,
			ADCBF,
			ADCBI,
			ADCBST,
			ADCBT,
			ADCBTST,
			ADCBZ,
			ASYNC,
			ATLBSYNC,
			APTESYNC,
			ALWSYNC,
			ATW,
			AWORD,
			ARFI,
			ARFCI,
			ARFID,
			AHRFID:

§EcBSizeÒ §EcIndex ¦EcDistœ ¨CSumAlgo ¨PartNums‘ ©PartETagsÀ©PartSizes‘Ñ ŠªPartASizes‘Ñ Š¤SizeÑ Š¥MTimeÓ É ž³í §MetaSys ¼x-minio-internal-inline-dataÄ true§MetaUsr‚¤etagÙ 481841022d5df9056cb9¬content-type¸application/octet-stream¡v Î¥ x ¤nullÄ4.<É“àté >Cbf¯¼Ç^&æ+ Ï' „x ¤1t þ¿öO’ š§½m£°y]ËyBT¾Œ multisitea/data/disterasure/xl4/.minio.sys/buckets/.bloomcycle.bin/xl.meta XL2 Æ w Ä$•Ä Ó É Ÿ9æ€Ä -HN Å Kƒ¤Type ¥V2ObjÞ ¢IDÄ ¤DDirÄ á x ÒE—¢_ _xÏS1¦EcAlgo £EcM £EcN §EcBSizeÒ §EcIndex ¦EcDistœ ¨CSumAlgo ¨PartNums‘...

		v.AddArg(v0)
		return true
	}
}
func rewriteValuePPC64_OpPrefetchCache(v *Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (PrefetchCache ptr mem)
	// result: (DCBT ptr mem [0])
	for {
		ptr := v_0
		mem := v_1
		v.reset(OpPPC64DCBT)
		v.AuxInt = int64ToAuxInt(0)
		v.AddArg2(ptr, mem)
		return true
	}
}

## Dependencies

### Added
_Nothing has changed._

### Changed
- sigs.k8s.io/apiserver-network-proxy/konnectivity-client: v0.0.35 → v0.0.36