LSR $32, acc2, t0 MUL acc2, const1, t1 UMULH acc2, const1, acc2 ADCS t0, acc0 ADCS t1, acc1 ADC $0, acc2 // Last reduction step ADDS acc3<<32, acc0, acc0 LSR $32, acc3, t0 MUL acc3, const1, t1 UMULH acc3, const1, acc3 ADCS t0, acc1 ADCS t1, acc2 ADC $0, acc3 SUBS $-1, acc0, t0 SBCS const0, acc1, t1 SBCS $0, acc2, t2 SBCS const1, acc3, t3 CSEL CS, t0, acc0, acc0 CSEL CS, t1, acc1, acc1 CSEL CS, t2, acc2, acc2 CSEL CS, t3, acc3, acc3 STP (acc0, acc1), 0*16(res_ptr) STP (acc2, acc3), 1*16(res_ptr) RET...

                }
            }.orElse(provider {
                throw GradleException("Expected boolean flag to be configured")
            })
        }
        .reduce { acc, next ->
            acc.zip(next) { left, right ->
                when {
                    !left.isPresent -> right
                    !right.isPresent -> left