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src/cmd/asm/internal/asm/testdata/loong64enc1.s
VROTRV V1, V2, V3 // 4384ef70 XVSLLB X3, X2, X1 // 410ce874 XVSLLH X3, X2, X1 // 418ce874 XVSLLW X3, X2, X1 // 410ce974 XVSLLV X3, X2, X1 // 418ce974 XVSRLB X3, X2, X1 // 410cea74 XVSRLH X3, X2, X1 // 418cea74 XVSRLW X3, X2, X1 // 410ceb74 XVSRLV X3, X2, X1 // 418ceb74 XVSRAB X3, X2, X1 // 410cec74 XVSRAH X3, X2, X1 // 418cec74 XVSRAW X3, X2, X1 // 410ced74 XVSRAV X3, X2, X1 // 418ced74
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Thu Sep 04 19:24:25 UTC 2025 - 35.5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/asm.go
x1 := p.getConstant(prog, op, &a[1]) x2 := int64(p.getRegister(prog, op, &a[2])) x3 := int64(p.getRegister(prog, op, &a[3])) x4 := int64(p.getRegister(prog, op, &a[4])) x5 := p.getConstant(prog, op, &a[5]) // Cond is handled specially for this instruction. offset, MRC, ok := arch.ARMMRCOffset(op, cond, x0, x1, x2, x3, x4, x5) if !ok { p.errorf("unrecognized condition code .%q", cond) }
Registered: Tue Sep 09 11:13:09 UTC 2025 - Last Modified: Tue Aug 05 17:31:25 UTC 2025 - 26.2K bytes - Viewed (0)