VROTRV		V1, V2, V3	// 4384ef70
	XVSLLB		X3, X2, X1	// 410ce874
	XVSLLH		X3, X2, X1	// 418ce874
	XVSLLW		X3, X2, X1	// 410ce974
	XVSLLV		X3, X2, X1	// 418ce974
	XVSRLB		X3, X2, X1	// 410cea74
	XVSRLH		X3, X2, X1	// 418cea74
	XVSRLW		X3, X2, X1	// 410ceb74
	XVSRLV		X3, X2, X1	// 418ceb74
	XVSRAB		X3, X2, X1	// 410cec74
	XVSRAH		X3, X2, X1	// 418cec74
	XVSRAW		X3, X2, X1	// 410ced74
	XVSRAV		X3, X2, X1	// 418ced74

X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 ADDQ $0x20, CX enc128: MOVUPS (CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 16(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 32(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 48(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS 64(CX), X0 AESENC X0, X1 AESENC X0, X2 AESENC X0, X3 AESENC X0, X4 MOVUPS...

			x1 := p.getConstant(prog, op, &a[1])
			x2 := int64(p.getRegister(prog, op, &a[2]))
			x3 := int64(p.getRegister(prog, op, &a[3]))
			x4 := int64(p.getRegister(prog, op, &a[4]))
			x5 := p.getConstant(prog, op, &a[5])
			// Cond is handled specially for this instruction.
			offset, MRC, ok := arch.ARMMRCOffset(op, cond, x0, x1, x2, x3, x4, x5)
			if !ok {
				p.errorf("unrecognized condition code .%q", cond)
			}

	}
}

func archRISCV64(shared bool) *Arch {
	register := make(map[string]int16)

	// Standard register names.
	for i := riscv.REG_X0; i <= riscv.REG_X31; i++ {
		// Disallow X3 in shared mode, as this will likely be used as the
		// GP register, which could result in problems in non-Go code,
		// including signal handlers.
		if shared && i == riscv.REG_GP {
			continue
		}