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src/cmd/asm/internal/asm/testdata/riscv64validation.s
VFWCVTXUFV X10, V3 // ERROR "expected vector register in vs2 position" VFWCVTXFV X10, V3 // ERROR "expected vector register in vs2 position" VFWCVTRTZXUFV X10, V3 // ERROR "expected vector register in vs2 position" VFWCVTRTZXFV X10, V3 // ERROR "expected vector register in vs2 position" VFWCVTFXUV X10, V3 // ERROR "expected vector register in vs2 position" VFWCVTFXV X10, V3 // ERROR "expected vector register in vs2 position"
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 42.1K bytes - Viewed (0) -
tensorflow/c/c_api_function_test.cc
std::vector<TF_Output> out; for (auto op : ops) { out.push_back({op, 0}); } return out; } void Define(int num_opers, const std::vector<TF_Operation*>& opers, const std::vector<TF_Operation*>& inputs, const std::vector<TF_Operation*>& outputs, const std::vector<string>& output_names, bool expect_failure = false) {
Registered: Tue Dec 30 12:39:10 UTC 2025 - Last Modified: Mon Nov 17 00:00:38 UTC 2025 - 63.6K bytes - Viewed (1) -
src/cmd/asm/internal/asm/testdata/riscv64.s
// 31.11.15: Vector Integer Merge Instructions VMERGEVVM V1, V2, V0, V3 // d781205c VMERGEVXM X10, V2, V0, V3 // d741255c VMERGEVIM $15, V2, V0, V3 // d7b1275c // 31.11.16: Vector Integer Move Instructions VMVVV V2, V3 // d701015e VMVVX X10, V3 // d741055e VMVVI $15, V3 // d7b1075e // 31.12.1: Vector Single-Width Saturating Add and Subtract
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 13 12:17:37 UTC 2025 - 73.7K bytes - Viewed (0) -
tensorflow/c/c_api_test.cc
EXPECT_TRUE(found); TF_DeleteBuffer(op_list_buffer); } } void TestEncodeDecode(int line, const std::vector<string>& data) { const int64_t n = data.size(); absl::Status status; for (const std::vector<int64_t>& dims : std::vector<std::vector<int64_t>>{{n}, {1, n}, {n, 1}, {n / 2, 2}}) { // Create C++ Tensor Tensor src(tensorflow::DT_STRING, TensorShape(dims));
Registered: Tue Dec 30 12:39:10 UTC 2025 - Last Modified: Mon Nov 17 00:00:38 UTC 2025 - 97K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc1.s
VMOVQ V3.W[1], V7.W4 // 67e4f772 VMOVQ V4.V[0], V6.V2 // 86f0f772 // Move vector register to vector register. VMOVQ V1, V9 // 29002d73 VMOVQ V2, V8 // 48002d73 XVMOVQ X3, X7 // 67002d77 XVMOVQ X4, X6 // 86002d77 // Load data from memory and broadcast to each element of a vector register: VMOVQ offset(Rj), <Vd>.<T> VMOVQ (R4), V0.B16 // 80008030 VMOVQ 1(R4), V0.B16 // 80048030
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Thu Nov 27 00:46:52 UTC 2025 - 44.5K bytes - Viewed (0) -
tensorflow/c/checkpoint_reader.cc
: reader_(nullptr), v2_reader_(nullptr), var_to_shape_map_(nullptr), var_to_data_type_map_(nullptr) { // Depending on whether this is a V2 ckpt, initializes "reader_" or // "v2_reader_". std::vector<string> v2_path; if (Env::Default()->GetMatchingPaths(MetaFilename(filename), &v2_path).ok() && !v2_path.empty()) { v2_reader_.reset( new BundleReader(Env::Default(), filename /* prefix to a V2 ckpt */));
Registered: Tue Dec 30 12:39:10 UTC 2025 - Last Modified: Sat Nov 08 06:24:11 UTC 2025 - 5.4K bytes - Viewed (0) -
doc/asm.html
</p> <p> If a vector instruction takes a length or an index as an argument then it will be the first argument. For example, <code>VLEIF</code> <code>$1,</code> <code>$16,</code> <code>V2</code> will load the value sixteen into index one of <code>V2</code>. Care should be taken when using vector instructions to ensure that they are available at runtime.
Registered: Tue Dec 30 11:13:12 UTC 2025 - Last Modified: Fri Nov 14 19:09:46 UTC 2025 - 36.5K bytes - Viewed (0) -
docs/ru/docs/index.md
Registered: Sun Dec 28 07:19:09 UTC 2025 - Last Modified: Thu Dec 11 21:25:03 UTC 2025 - 32K bytes - Viewed (0) -
docs/es/docs/index.md
Registered: Sun Dec 28 07:19:09 UTC 2025 - Last Modified: Tue Dec 16 16:33:45 UTC 2025 - 24.3K bytes - Viewed (0) -
docs/pt/docs/index.md
Registered: Sun Dec 28 07:19:09 UTC 2025 - Last Modified: Tue Dec 16 20:32:40 UTC 2025 - 24.5K bytes - Viewed (0)